Change in coreboot[master]: soc/intel/xeon_sp/cpx: Work around FSP-M issues

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40555 )

Change subject: soc/intel/xeon_sp/cpx: Work around FSP-M issues
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soc/intel/xeon_sp/cpx: Work around FSP-M issues

Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.

TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB

Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/cpx/cpu.c
M src/soc/intel/xeon_sp/cpx/romstage.c
3 files changed, 14 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Maxim Polyakov: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 70703d0..88b0d5d 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -16,7 +16,6 @@
      select UDK_2015_BINDING
      select POSTCAR_CONSOLE
      select POSTCAR_STAGE
-	  select FSP_USES_CB_STACK

config FSP_HEADER_PATH
      string "Location of FSP headers"
@@ -40,11 +39,11 @@
 # currently FSP hardcodes [0fe800000;fe930000] for its heap
 config DCACHE_RAM_BASE
    hex
-	default 0xfe930000
+	default 0xfe9a0000

config DCACHE_RAM_SIZE
    hex
-	default 0xd0000
+	default 0x60000

config DCACHE_BSP_STACK_SIZE
    hex
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 8824686..a62c2f0 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -28,7 +28,7 @@

static void each_cpu_init(struct device *cpu)
 {
-	printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
+	printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
    	__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);

setup_lapic();
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index e909b87..355554a 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -9,8 +9,19 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;

(void)m_cfg;
+	/*
+	 * Currently FSP for CPX does not implement user-provided StackBase/Size
+	 * properly. When KTI link needs to be trained, inter-socket communication
+	 * library needs quite a bit of memory for its heap usage. However, location
+	 * is hardcoded so this workaround is needed.
+	 */
+	if (CONFIG_MAX_SOCKET > 1) {
+		arch_upd->StackBase = (void *) 0xfe930000;
+		arch_upd->StackSize = 0x70000;
+	}

mainboard_memory_init_params(mupd);
 }