Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 356 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/1
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 62d7f40..29b0e07 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2018 Angel Pons th3fanbus@gmail.com +## Copyright (C) 2018-2019 Angel Pons th3fanbus@gmail.com ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ##
-if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -31,7 +31,7 @@ select INTEL_GMA_HAVE_VBT select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V + select NO_UART_ON_SUPERIO if !BOARD_GIGABYTE_GA_H61M_S2PV
config MAINBOARD_DIR string @@ -40,11 +40,13 @@ config VARIANT_DIR string default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV + default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
config MAINBOARD_PART_NUMBER string default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV + default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
config DEVICETREE @@ -63,4 +65,4 @@ int default 2
-endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +endif # BOARD_GIGABYTE_GA_H61M* diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name index 83b5803..5951c82 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name @@ -1,5 +1,8 @@ config BOARD_GIGABYTE_GA_H61M_S2PV bool "GA-H61M-S2PV"
+config BOARD_GIGABYTE_GA_H61M_DS2V + bool "GA-H61M-DS2V" + config BOARD_GIGABYTE_GA_H61MA_D3V bool "GA-H61MA-D3V" diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb new file mode 100644 index 0000000..12c1301 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -0,0 +1,102 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0x0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe x1 Port (PCIEX1) + device pci 1c.1 off end # Unused PCIe Port + device pci 1c.2 off end # Unused PCIe Port + device pci 1c.3 off end # Unused PCIe Port + device pci 1c.4 on end # Realtek RTL8111F Ethernet Controller + device pci 1c.5 off end # Unused PCIe Port + device pci 1c.6 off end # Unused PCIe Port + device pci 1c.7 off end # Unused PCIe Port + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + irq 0xf1 = 0x80 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0xf0 = 0x08 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c new file mode 100644 index 0000000..89bc4d6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c new file mode 100644 index 0000000..33c3492 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 0x0000000f, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 1: Code-Review+1
(10 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 4: ## Copyright (C) 2018-2019 Angel Pons th3fanbus@gmail.com Did you add new, creative work, this year?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 34: select NO_UART_ON_SUPERIO if !BOARD_GIGABYTE_GA_H61M_S2PV Would be much easier to read without the inversion.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 17: register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3" Is this useful?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: register "c1_battery" = "1" Will the *battery values ever be used?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 70: irq 0xf1 = 0x80 Does this work? I see no entry for this in the respective `superio.c`, but there could be.
Please test after removing all power including the CMOS battery if there is any doubt.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08 Does this work? I see no entry for this in the respective `superio.c`, but there could be.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 79: irq 0x25 = 0x40 : irq 0x26 = 0xf7 : irq 0x27 = 0x10 : irq 0x2c = 0x80 Does this work?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 87: irq 0xc1 = 0x37 : irq 0xcb = 0x00 Does this work?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 89: irq 0xf0 = 0x10 : irq 0xf1 = 0x42 : irq 0xf6 = 0x1c Does this work? I see no entries for these in the respective `superio.c`, but there could be.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: 0x0000000f, /* Number of 4 dword sets */ Why write the number in hex? makes review harder.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 1:
(11 comments)
I think some of the comments also apply to the other variants already in the tree. Since the floor hasn't collapsed yet, I'm pretty sure I still have the other boards buried somewhere inside this room. If I find them, I'll boot-test the entire family.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 4: ## Copyright (C) 2018-2019 Angel Pons th3fanbus@gmail.com
Did you add new, creative work, this year?
Yes, I added two boards into this part of the tree this year, but most of the work is not on this file. I guess Gigabyte designers were rather lazy when designing these boards, and made them very similar. Want me to add some ASCII art of watermelons to make up for it?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 34: select NO_UART_ON_SUPERIO if !BOARD_GIGABYTE_GA_H61M_S2PV
Would be much easier to read without the inversion.
I agree. Handling negative Kconfig symbols (that is, symbols that represent the *absence* of something) is cumbersome. So, do you have any plans to flip that symbol?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 17: register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3"
Is this useful?
Autoport adds this. At least ndid matches the length of the did array :D
In any case, this does not seem particularly useful. The real question is, does *any* board need these? I think it's just dead code in 90% of all snb/ivb boards
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: register "c1_battery" = "1"
Will the *battery values ever be used?
Don't give me ideas... I don't think so, but I have not checked what would happen if they are omitted.
In any case, only a few boards should need special values here, so why not have sane defaults in the CPU code instead?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 44: device pci 16.0 on end # Management Engine Interface 1 Can drop some unused devices
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 70: irq 0xf1 = 0x80
Does this work? I see no entry for this in the respective `superio.c`, […]
About bit 7: This bit is set to 1 when AVCC3 is on at the previous AC power failure whereas 0 when AVCC3 is off.
I guess it's not needed.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
Does this work? I see no entry for this in the respective `superio.c`, […]
This writes the default value, just like the two `io` lines right above. Do I drop only this, or the three lines?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 79: irq 0x25 = 0x40 : irq 0x26 = 0xf7 : irq 0x27 = 0x10 : irq 0x2c = 0x80
Does this work?
Yes? I even removed the CMOS battery and went back to 2010 for a while.
These are muxing GPIOs and such, so without looking at the schematics I'd rather not risk it.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 87: irq 0xc1 = 0x37 : irq 0xcb = 0x00
Does this work?
Yes?
Is it needed? Maybe not, but I'm not sure if I have schematics to check what these GPIOs do.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 89: irq 0xf0 = 0x10 : irq 0xf1 = 0x42 : irq 0xf6 = 0x1c
Does this work? I see no entries for these in the respective `superio.c`, […]
Yes? I even removed the CMOS battery and went back to 2010 for a while.
0xf0: SMI# control register 1. Enables the Environmental Controller IRQs to generate SMIs. 0xf1: SMI# control register 2. Sets level trigger and enables the WDT IRQs to generate SMIs. 0xf6: Alert beep pin location.
Maybe I don't need these when I don't care the slightest about SMIs, but played safe and mirrored vendor because this is the GPIO LDN.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: 0x0000000f, /* Number of 4 dword sets */
Why write the number in hex? makes review harder.
Ask autoport about it, maybe that pile of Go code likes the alignment that 8-nibble hex quantities provide? I'm pretty sure there's at least two dozen boards in the tree which do the exact same thing.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 4: ## Copyright (C) 2018-2019 Angel Pons th3fanbus@gmail.com
Yes, I added two boards into this part of the tree this year, but most of the work is not on this fi […]
Well, the copyright notice refers to _this_ file. ASCII art much appreciated ;) I wonder how recognizable a watermelon would be in ASCII ^^
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 34: select NO_UART_ON_SUPERIO if !BOARD_GIGABYTE_GA_H61M_S2PV
I agree. […]
No plans beyond the this-should-have-been-done-from-the-beginning. We could flip it. But all the boards that currently don't select NO_UART_ON_SUPERIO by accident would then select the UART driver which would make it look like we explicitly expect a UART that isn't there. The usual problem of incomplete ports because there was no measure to explicitly state what is on the board. (for most boards the information might still be discoverable on the web, but that's a lot of work to check for it)
Anyway, I meant the ! in that line. I'm used to the NO_UART already that I didn't even notice the double negative. If one reads the line long enough, it's clearly selecting UART for the S2PV which makes sense.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 17: register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3"
Autoport adds this. At least ndid matches the length of the did array :D […]
IIRC, it's useful to cycle through the available displays and might matter on laptops that have a special key for it. Never tested if it really works, though.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: register "c1_battery" = "1"
Don't give me ideas... […]
Sane defaults sounds very reasonable.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 70: irq 0xf1 = 0x80
About bit 7: […]
Sorry, I was confused by the absence of the PNP_MSC* resources in `superio.c`. Again, I read the `pnp_device.c` and come to the conclusion that they are only necessary for proper warning display.
NB. After all, `pnp_device.c` implements some nice ideas. But together with the pecularities of our allocator, it seems to cause more errors and confusion to register the resources in `superio.c` (see `io` lines below, for instance).
About the bit, sounds like it would be status, hence read-only, doesn't it?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
This writes the default value, just like the two `io` lines right above. […]
You can't drop the `io` lines. These resources are registered in `superio.c`. The allocator would try to assign them (and likely fail).
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 87: irq 0xc1 = 0x37 : irq 0xcb = 0x00
Yes? […]
Ack
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 89: irq 0xf0 = 0x10 : irq 0xf1 = 0x42 : irq 0xf6 = 0x1c
Yes? I even removed the CMOS battery and went back to 2010 for a while. […]
Ack
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37483
to look at the new patch set (#2).
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 343 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 17: register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3"
IIRC, it's useful to cycle through the available displays and might matter […]
Killed it
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 44: device pci 16.0 on end # Management Engine Interface 1
Can drop some unused devices
Took out some trash.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 70: irq 0xf1 = 0x80
Sorry, I was confused by the absence of the PNP_MSC* resources in `superio.c`. […]
Killed 0xf1, should I kill the rest as well?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
You can't drop the `io` lines. These resources are registered in `superio.c`. […]
Killed.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: 0x0000000f, /* Number of 4 dword sets */
Ask autoport about it, maybe that pile of Go code likes the alignment that 8-nibble hex quantities p […]
Denarified the figure.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
Killed.
We might be talking past each other: If the `superio.c` registers i/o resources _and_ the LDN is enabled here without setting these resources, the allocator will try to assign them. However, it does a shitty job and usually breaks i/o allocation for PCI devices while doing so.
Please check if you see any i/o resource related errors in the log.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... PS2, Line 23: 0x2 2 ? see #37849
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
We might be talking past each other: If the `superio.c` registers […]
I think I misread several things. So, if I understand correctly, the `io` lines must stay, because they are in `superio.c`.
However, was your original comment referring to these, or was it referring to the `irq` line instead?
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... PS2, Line 23: 0x2
2 ? […]
If you want to refer a Gerrit change, you can use: CB:37849
That way, lazy people like me can click on it right away :P
But yes, I will change these numbers
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37483
to look at the new patch set (#3).
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 346 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/37483/2/src/mainboard/gigabyte/ga-h... PS2, Line 23: 0x2
If you want to refer a Gerrit change, you can use: CB:37849 […]
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 3: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
I think I misread several things. […]
Original comments were about the `irq` used for 0xf* registers. But I was wrong about them... they don't need an entry in `superio.c`.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 3: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 22: register "c1_battery" = "1"
Sane defaults sounds very reasonable.
Ack
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 58: device pci 1c.7 off end # Unused PCIe Port Doesn't this mean that they stay enabled?
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 75: irq 0xf0 = 0x08
Original comments were about the `irq` used for 0xf* registers. But I was […]
Done
Hello Patrick Rudolph, HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37483
to look at the new patch set (#4).
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 346 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 4: ## Copyright (C) 2018-2019 Angel Pons th3fanbus@gmail.com
Well, the copyright notice refers to _this_ file. ASCII art much appreciated ;) […]
Done
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 34: select NO_UART_ON_SUPERIO if !BOARD_GIGABYTE_GA_H61M_S2PV
No plans beyond the this-should-have-been-done-from-the-beginning. We could […]
Done
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 58: device pci 1c.7 off end # Unused PCIe Port
Doesn't this mean that they stay enabled?
These don't exist on H61, so they won't ever be enabled I guess
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Feel free to fill the commit message with what was tested.
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... PS4, Line 10: select NO_UART_ON_SUPERIO I don't think this belongs into Kconfig.name; but don't know any hard rules about it either.
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/1/src/mainboard/gigabyte/ga-h... PS1, Line 58: device pci 1c.7 off end # Unused PCIe Port
These don't exist on H61, so they won't ever be enabled I guess
TIL
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... PS4, Line 10: select NO_UART_ON_SUPERIO
I don't think this belongs into Kconfig.name; but don't know any hard rules […]
It's rather unusual, but it keeps Kconfig cleaner
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 4:
(1 comment)
Patch Set 4: Code-Review+2
(2 comments)
Feel free to fill the commit message with what was tested.
I'll do that as soon as I have the board with me again (Jan 6). Wrote up a draft in a comment, which also doubles as a submit-lock.
https://review.coreboot.org/c/coreboot/+/37483/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37483/4//COMMIT_MSG@9 PS4, Line 9: Took less than 30 minutes, and booted on the first try :) FIXME: Test things and list them here
Off the top of my head:
Working: libgfxinit, usbdebug, some USB ports, some SATA ports, integrated LAN, both DIMMs, SeaBIOS
TESTME: audio, PCIe slots, double-check both VGA and DVI work, test all USB and SATA ports (for the sake of completeness), S3 resume (probably works just fine), PS/2 ports, another payload (for the sake of completeness)
note to self: you have a Broadcom PCIe x1 card in the shoe box with the Asrock Q1900M, so you don't need to tear down graphite to use its wireless card.
Hello Patrick Rudolph, HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37483
to look at the new patch set (#6).
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Working: - S3 suspend/resume - USB ports and headers - EHCI Debug with a FT2232H - Gigabit Ethernet - Integrated DVI/VGA graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Native raminit (2+2GB DDR3-1333) - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested.
Untested: - VGA BIOS for integrated graphics init - Audio: Only front/rear outputs have been tested. - Non-Linux OSes - ACPI thermal zone and OS-independent fan control
Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 350 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37483/4//COMMIT_MSG@9 PS4, Line 9: Took less than 30 minutes, and booted on the first try :)
FIXME: Test things and list them here […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@14 PS6, Line 14: a an? (depends on how you pronounce FT2232H)
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@27 PS6, Line 27: - Audio: Only front/rear outputs have been tested. What other outputs are there?
https://review.coreboot.org/c/coreboot/+/37483/6/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/6/src/mainboard/gigabyte/ga-h... PS6, Line 93: device pci 1f.6 on end # Thermal What difference does it make? Does Linux have a driver for it that does something on its own?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 6: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@14 PS6, Line 14: a
an? (depends on how you pronounce FT2232H)
Oops
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@27 PS6, Line 27: - Audio: Only front/rear outputs have been tested.
What other outputs are there?
No other outputs, but the inputs are untested. I'll reword this a bit.
https://review.coreboot.org/c/coreboot/+/37483/6/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37483/6/src/mainboard/gigabyte/ga-h... PS6, Line 93: device pci 1f.6 on end # Thermal
What difference does it make? Does Linux have a driver for it that does […]
I'm not sure, I have it enabled on the GA-H61MA-D3V but not on the GA-H61M-S2PV.
After this gets merged, I want to switch these boards to overridetrees, so I'll check if this provides any advantage.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Arthur Heymans, Patrick Rudolph, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37483
to look at the new patch set (#7).
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested.
Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control
Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 350 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37483/7
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@14 PS6, Line 14: a
Oops
Done
https://review.coreboot.org/c/coreboot/+/37483/6//COMMIT_MSG@27 PS6, Line 27: - Audio: Only front/rear outputs have been tested.
No other outputs, but the inputs are untested. I'll reword this a bit.
Done
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... PS4, Line 10: select NO_UART_ON_SUPERIO
It's rather unusual, but it keeps Kconfig cleaner
This is a very old discussion, but I'm not sure that we should split options between files like that.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37483/4/src/mainboard/gigabyte/ga-h... PS4, Line 10: select NO_UART_ON_SUPERIO
This is a very old discussion, but I'm not sure that we should split options between files like that […]
It's a rather common pattern by now. Which puts the discussion out of this change's scope.
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :)
Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested.
Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control
Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c 5 files changed, 350 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 62c422a..18982c8 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ##
-if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -30,7 +30,6 @@ select INTEL_GMA_HAVE_VBT select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V
config MAINBOARD_DIR string @@ -39,11 +38,13 @@ config VARIANT_DIR string default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV + default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
config MAINBOARD_PART_NUMBER string default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV + default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
config DEVICETREE @@ -62,4 +63,4 @@ int default 2
-endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V +endif # BOARD_GIGABYTE_GA_H61M* diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name index 83b5803..15d107d 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name @@ -1,5 +1,10 @@ config BOARD_GIGABYTE_GA_H61M_S2PV bool "GA-H61M-S2PV"
+config BOARD_GIGABYTE_GA_H61M_DS2V + bool "GA-H61M-DS2V" + select NO_UART_ON_SUPERIO + config BOARD_GIGABYTE_GA_H61MA_D3V bool "GA-H61MA-D3V" + select NO_UART_ON_SUPERIO diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb new file mode 100644 index 0000000..2cc5b19 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/devicetree.cb @@ -0,0 +1,96 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3) + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2) + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c new file mode 100644 index 0000000..89bc4d6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c new file mode 100644 index 0000000..1379b1a --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37483 )
Change subject: mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1182 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1181 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1180
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)