Change in coreboot[master]: mb/asus/p5qc: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

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HAOUAS Elyes (Code Review)

9 Nov 2019 9 Nov '19

12:06 a.m.

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36693 )

Change subject: mb/asus/p5qc: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

mb/asus/p5qc: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/asus/p5qc/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36693/1

diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 1477d80..fb30bee 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -23,7 +23,6 @@ #include <arch/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> -#include <northbridge/intel/x4x/iomap.h>

#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0)

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Arthur Heymans (Code Review)

9 Nov 9 Nov

12:09 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36693 )

Change subject: mb/asus/p5qc: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

Patch Set 1: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/36693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Gerrit-Change-Number: 36693 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Comment-Date: Sat, 09 Nov 2019 07:09:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

12:30 a.m.

New subject: Change in coreboot[master]: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Hello Angel Pons, Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36693

to look at the new patch set (#2).

Change subject: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c 8 files changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36693/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/36693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Gerrit-Change-Number: 36693 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

12:42 a.m.

New subject: Change in coreboot[master]: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36693 )

Change subject: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

Patch Set 2: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/36693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Gerrit-Change-Number: 36693 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sat, 09 Nov 2019 07:42:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

3:42 a.m.

New subject: Change in coreboot[master]: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36693 )

Change subject: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

Patch Set 2: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/36693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Gerrit-Change-Number: 36693 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Sat, 09 Nov 2019 10:42:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

11 Nov 11 Nov

3:29 a.m.

New subject: Change in coreboot[master]: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36693 )

Change subject: mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>' ......................................................................

mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'

Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/36693 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c 8 files changed, 0 insertions(+), 8 deletions(-)

Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index bb7a342..57d1ec2 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <arch/romstage.h> -#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 1477d80..fb30bee 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -23,7 +23,6 @@ #include <arch/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> -#include <northbridge/intel/x4x/iomap.h>

#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 30480ad..2836bf7 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -22,7 +22,6 @@ #include <arch/romstage.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> -#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 0bfbbfe..01473c8 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <arch/romstage.h> #include <device/pci_ops.h> -#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d4ce940..8ba173e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -25,7 +25,6 @@ #include <arch/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> -#include <northbridge/intel/x4x/iomap.h>

#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 81d5067..a6969ad 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <arch/romstage.h> -#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 8207638..018df1b 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -23,7 +23,6 @@ #include <arch/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> -#include <northbridge/intel/x4x/iomap.h>

#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index cb84ce0..10889a9 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -23,7 +23,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include <northbridge/intel/x4x/iomap.h>

#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0)

-- To view, visit https://review.coreboot.org/c/coreboot/+/36693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Gerrit-Change-Number: 36693 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: merged

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Angel Pons (Code Review)
Arthur Heymans (Code Review)
HAOUAS Elyes (Code Review)
Patrick Georgi (Code Review)