Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration

[Furquan Shaikh (Code Review)]

Attention is currently required from: Bhanu Prakash Maiya, Ivy Jian, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 )

Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration
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Patch Set 9:

(1 comment)

File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/52181/comment/0346e8d9_62fb4587 
PS9, Line 113: register "has_power_resource" = "1"
> This will not work for FPMCU. We want FPMCU to be kept enabled in S3 and S0i3 states. […]

Thinking about this some more:

There are two suspend mechanisms: S3 and S0i3

In case of S3, coreboot gets to run on resume path(on x86). In case of S0i3, coreboot does not run on resume path(on x86). FPMCU needs to retain power across suspend/resume both for S3 and S0i3.

Few questions to check on:
1. Are the signals GPIO_11(reset) and GPIO_32(enable) driven low at reset? This is important to ensure that the FPMCU starts with power-turned off when coming out of reset.
2. Do the GPIOs retain state in S3 and S0i3?

The way this can be handled is:

1. Configure GPIO_32 to enable power in bootblock gpio table (variant_bootblock_gpio_table()).

2. Configure GPIO_11 to deassert reset in ramstage gpio table (mainboard_configure_gpios() -> variant_base_gpio_table()).

3. Your device tree node can be the same as it was before i.e. without has_power_resource.

Since enable and reset pads are configured in bootblock and ramstage, the 3ms delay should automatically be satisfied. The way this will work is:

1. Enable and reset signals are driven low coming out of reset.
2. When booting out of S5/G3, enable is driven high in bootblock, followed by deassertion of reset in ramstage. This satisfies the sequencing requirement.
3. When going into S3 or S0i3,the signals will retain state.
4. On S3 resume, coreboot will go through bootblock and ramstage, but it only drives the signals high. So, no change in signal state.
5. On S0i3 resume, coreboot on x86 is not involved. So, no change in signal state.