Change in coreboot[master]: mainboard/google/fizz: Enable Devslp for SATA port 1

[Gaggery Tsai (Code Review)]

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/21765

Change subject: mainboard/google/fizz: Enable Devslp for SATA port 1
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mainboard/google/fizz: Enable Devslp for SATA port 1

This patch is to enable the support of device sleep
for SATA port 1.

BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.

Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai 
---
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/fizz/gpio.h
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21765/1

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index ead880e..8f5c49f 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -30,8 +30,8 @@
    register "EnableSata" = "1"
    register "SataSalpSupport" = "1"
    register "SataMode" = "1"
-	register "SataPortsEnable[0]" = "1"
    register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[1]" = "1"
    register "EnableAzalia" = "1"
    register "DspEnable" = "1"
    register "IoBufferOwnership" = "3"
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 13081ec..d9f1bd8 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -167,7 +167,7 @@
 /* SATAXPCIE2 */	PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
    			   NF1), /* DB_PCIE_SATA#_DET */
 /* CPU_GP0 */		PAD_CFG_NC(GPP_E3),
-/* SATA_DEVSLP0 */	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */
+/* SATA_DEVSLP0 */	PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* DEVSLP0_MB */
 /* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
 /* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6), /* TP328 */
 /* CPU_GP1 */		PAD_CFG_NC(GPP_E7),