Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50487 )
Change subject: soc/amd/cezanne: select soc-specific APCI functionality ......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/50487/comment/58924813_00178549 PS2, Line 16: uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ : uint8_t lids; /* 0x01 - LID State */ : uint8_t pwrs; /* 0x02 - AC Power State */ : uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ : uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ : uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ : uint8_t tmps; /* 0x17 - Temperature Sensor ID */ : uint8_t tcrt; /* 0x18 - Critical Threshold */ : uint8_t tpsv; /* 0x19 - Passive Threshold */
do we need all of these?
no, we dont. it's a copy from picasso right now. do you want me to remove the unneeded fields? part of the reason to keep it like it is right now is also that Kyösti has some patches in that area in review, so it might be helpful, if there isn't any unnecessary change here. if you really want me to only add what's strictly necessary, i can remove the rest from the patch though
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Felix Held (Code Review)