Change in coreboot[master]: riscv: add physical memory protection (PMP) support

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28569 )

Change subject: riscv: add physical memory protection (PMP) support
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Patch Set 4:

(4 comments)

https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c
File src/arch/riscv/pmp.c:

https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@24
PS4, Line 24: /* 
trailing whitespace

https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@32
PS4, Line 32:          * When generating a TOR type configuration,
code indent should use tabs where possible

https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@34
PS4, Line 34: 	 * used to record the value of pmpaddr[i - 1] 
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https://review.coreboot.org/#/c/28569/4/src/arch/riscv/pmp.c@35
PS4, Line 35:          */
code indent should use tabs where possible