Change in ...coreboot[master]: soc/intel/skylake: Define VR settings

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Roy Mingi Park (Code Review)

13 Feb 2019 13 Feb '19

4:11 a.m.

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31381

Change subject: soc/intel/skylake: Define VR settings ......................................................................

soc/intel/skylake: Define VR settings

Define VR settings configuration as per board design.

BUG=N/A TEST=Build and boot up into sarien platform.

Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 48 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31381/1

diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7..dfb807f 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -19,7 +19,54 @@ #include <soc/vr_config.h>

static const struct vr_config default_configs[NUM_VR_DOMAINS] = { - /* TODO: define this*/ + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, };

void fill_vr_domain_config(void *params,

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build bot (Jenkins) (Code Review)

13 Feb 13 Feb

4:11 a.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31381 )

Change subject: soc/intel/skylake: Define VR settings ......................................................................

Patch Set 1:

(88 comments)

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c File src/soc/intel/cannonlake/vr_config.c:

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 22: [VR_SYSTEM_AGENT] = { please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 23: .vr_config_enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 23: .vr_config_enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 24: .psi1threshold = VR_CFG_AMP(20), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 24: .psi1threshold = VR_CFG_AMP(20), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 25: .psi2threshold = VR_CFG_AMP(5), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 25: .psi2threshold = VR_CFG_AMP(5), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 26: .psi3threshold = VR_CFG_AMP(1), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 26: .psi3threshold = VR_CFG_AMP(1), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 27: .psi3enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 27: .psi3enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 28: .psi4enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 28: .psi4enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 29: .imon_slope = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 29: .imon_slope = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 30: .imon_offset = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 30: .imon_offset = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 31: .icc_max = VR_CFG_AMP(6), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 31: .icc_max = VR_CFG_AMP(6), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 32: .voltage_limit = 1520, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 32: .voltage_limit = 1520, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 33: }, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 34: [VR_IA_CORE] = { please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 35: .vr_config_enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 35: .vr_config_enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 36: .psi1threshold = VR_CFG_AMP(20), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 36: .psi1threshold = VR_CFG_AMP(20), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 37: .psi2threshold = VR_CFG_AMP(5), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 37: .psi2threshold = VR_CFG_AMP(5), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 38: .psi3threshold = VR_CFG_AMP(1), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 38: .psi3threshold = VR_CFG_AMP(1), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 39: .psi3enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 39: .psi3enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 40: .psi4enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 40: .psi4enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 41: .imon_slope = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 41: .imon_slope = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 42: .imon_offset = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 42: .imon_offset = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 43: .icc_max = VR_CFG_AMP(70), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 43: .icc_max = VR_CFG_AMP(70), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 44: .voltage_limit = 1520, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 44: .voltage_limit = 1520, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 45: }, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 46: [VR_GT_UNSLICED] = { please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 47: .vr_config_enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 47: .vr_config_enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 48: .psi1threshold = VR_CFG_AMP(20), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 48: .psi1threshold = VR_CFG_AMP(20), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 49: .psi2threshold = VR_CFG_AMP(5), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 49: .psi2threshold = VR_CFG_AMP(5), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 50: .psi3threshold = VR_CFG_AMP(1), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 50: .psi3threshold = VR_CFG_AMP(1), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 51: .psi3enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 51: .psi3enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 52: .psi4enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 52: .psi4enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 53: .imon_slope = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 53: .imon_slope = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 54: .imon_offset = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 54: .imon_offset = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 55: .icc_max = VR_CFG_AMP(31), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 55: .icc_max = VR_CFG_AMP(31), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 56: .voltage_limit = 1520, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 56: .voltage_limit = 1520, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 57: }, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 58: [VR_GT_SLICED] = { please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 59: .vr_config_enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 59: .vr_config_enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 60: .psi1threshold = VR_CFG_AMP(20), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 60: .psi1threshold = VR_CFG_AMP(20), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 61: .psi2threshold = VR_CFG_AMP(5), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 61: .psi2threshold = VR_CFG_AMP(5), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 62: .psi3threshold = VR_CFG_AMP(1), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 62: .psi3threshold = VR_CFG_AMP(1), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 63: .psi3enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 63: .psi3enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 64: .psi4enable = 1, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 64: .psi4enable = 1, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 65: .imon_slope = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 65: .imon_slope = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 66: .imon_offset = 0x0, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 66: .imon_offset = 0x0, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 67: .icc_max = VR_CFG_AMP(31), code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 67: .icc_max = VR_CFG_AMP(31), please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 68: .voltage_limit = 1520, code indent should use tabs where possible

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 68: .voltage_limit = 1520, please, no spaces at the start of a line

https://review.coreboot.org/#/c/31381/1/src/soc/intel/cannonlake/vr_config.c... PS1, Line 69: }, please, no spaces at the start of a line

-- To view, visit https://review.coreboot.org/c/coreboot/+/31381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Gerrit-Change-Number: 31381 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Roy Mingi Park roy.mingi.park@intel.com Gerrit-CC: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 13 Feb 2019 04:11:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Roy Mingi Park (Code Review)

4:16 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31381

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Define VR settings ......................................................................

soc/intel/skylake: Define VR settings

Define VR settings configuration as per board design.

BUG=N/A TEST=Build and boot up into sarien platform.

Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 48 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31381/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/31381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Gerrit-Change-Number: 31381 Gerrit-PatchSet: 2 Gerrit-Owner: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Roy Mingi Park (Code Review)

4:17 a.m.

New subject: Change in ...coreboot[master]: soc/intel/cannonlake: Define VR settings

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31381

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: Define VR settings ......................................................................

soc/intel/cannonlake: Define VR settings

Define VR settings configuration as per board design.

BUG=N/A TEST=Build and boot up into sarien platform.

Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Signed-off-by: Roy Mingi Park roy.mingi.park@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 48 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31381/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/31381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Gerrit-Change-Number: 31381 Gerrit-PatchSet: 3 Gerrit-Owner: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Roy Mingi Park (Code Review)

6:56 p.m.

New subject: Change in ...coreboot[master]: soc/intel/cannonlake: Define VR settings

Roy Mingi Park has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31381 )

Change subject: soc/intel/cannonlake: Define VR settings ......................................................................

Abandoned

-- To view, visit https://review.coreboot.org/c/coreboot/+/31381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3269a07dd4cb17d957ee0378b50bd3a23dcdc576 Gerrit-Change-Number: 31381 Gerrit-PatchSet: 3 Gerrit-Owner: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Roy Mingi Park roy.mingi.park@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: abandon

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