Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32467
Change subject: soc/skl: set IGD resources only if its is enabled ......................................................................
soc/skl: set IGD resources only if its is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space.
Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card.
The following boards were used for testing:
- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU.
Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS)
- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.
Payload: tianocore edk2-stable201811-216-g51be9d0.
Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 34 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32467/1
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 8e53f54..d7dec65 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -48,9 +48,17 @@
bool soc_is_vtd_capable(void);
-static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = { + GFXVTBAR, + GFXVT_BASE_ADDRESS, + GFXVT_BASE_SIZE, + "GFXVTBAR" };
+static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { + VTVC0BAR, + VTVC0_BASE_ADDRESS, + VTVC0_BASE_SIZE, + "VTVC0BAR" +}; #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index dcfc363..c4b872a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -263,14 +263,6 @@ int i; uint32_t mask = 0;
- /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. - */ - m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -310,12 +302,21 @@ * the FSP does not initialize this device */ m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; if (config->PrimaryDisplay == Display_iGFX) m_cfg->PrimaryDisplay = Display_Auto; else m_cfg->PrimaryDisplay = config->PrimaryDisplay; } else { m_cfg->InternalGfx = 1; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->PrimaryDisplay = config->PrimaryDisplay; } } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00a2782..71a9bee 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,11 +26,12 @@
static void systemagent_vtd_init(void) { - const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL;
- if (dev) - config = dev->chip_info; + if (root_dev) + config = root_dev->chip_info; if (config && config->ignore_vtd) return;
@@ -39,7 +40,10 @@ if (!vtd_capable) return;
- sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); + if (igd_dev && igd_dev->enabled) + sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1); + + sa_set_mch_bar(&soc_vtvc0_mmio_descriptor, 1); }
void systemagent_early_init(void) diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index fa0cd5e..70c85a0 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -42,6 +42,7 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { + struct device *const igd_dev = SA_DEV_IGD; static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -57,8 +58,11 @@ ARRAY_SIZE(soc_fixed_resources));
if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, - ARRAY_SIZE(soc_vtd_resources)); + { + if (igd_dev && igd_dev->enabled) + sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1); + } }
/*
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32467 )
Change subject: soc/skl: set IGD resources only if its is enabled ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/romstage/romst... File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/romstage/romst... PS1, Line 313: * Set IGD stolen size to 64MB. The FBC hardware for skylake does not line over 80 characters
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/romstage/romst... PS1, Line 314: * have access to the bios_reserved range so it always assumes 8MB is line over 80 characters
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/romstage/romst... PS1, Line 315: * used and so the kernel will avoid the last 8MB of the stolen window. line over 80 characters
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/romstage/romst... PS1, Line 316: * With the default stolen size of 32MB(-8MB) there is not enough space line over 80 characters
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/systemagent.c File src/soc/intel/skylake/systemagent.c:
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/systemagent.c@... PS1, Line 60: if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) that open brace { should be on the previous line
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/systemagent.c@... PS1, Line 63: sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); line over 80 characters
https://review.coreboot.org/#/c/32467/1/src/soc/intel/skylake/systemagent.c@... PS1, Line 64: sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1); line over 80 characters
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32467
to look at the new patch set (#2).
Change subject: soc/skl: set IGD resources only if its is enabled ......................................................................
soc/skl: set IGD resources only if its is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space.
Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card.
The following boards were used for testing:
- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU.
Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS)
- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.
Payload: tianocore edk2-stable201811-216-g51be9d0.
Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 38 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32467/2
Hello Patrick Rudolph, Angel Pons, Matt DeVillier, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32467
to look at the new patch set (#3).
Change subject: soc/skl: set IGD resources only if device is enabled ......................................................................
soc/skl: set IGD resources only if device is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space.
Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card.
The following boards were used for testing:
- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU.
Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS)
- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.
Payload: tianocore edk2-stable201811-216-g51be9d0.
Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 38 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32467/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32467 )
Change subject: soc/skl: set IGD resources only if device is enabled ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32467 )
Change subject: soc/skl: set IGD resources only if device is enabled ......................................................................
soc/skl: set IGD resources only if device is enabled
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space.
Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card.
The following boards were used for testing:
- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU.
Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS)
- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.
Payload: tianocore edk2-stable201811-216-g51be9d0.
Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 38 insertions(+), 18 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 8e53f54..d7dec65 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -48,9 +48,17 @@
bool soc_is_vtd_capable(void);
-static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, +static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = { + GFXVTBAR, + GFXVT_BASE_ADDRESS, + GFXVT_BASE_SIZE, + "GFXVTBAR" };
+static const struct sa_mmio_descriptor soc_vtvc0_mmio_descriptor = { + VTVC0BAR, + VTVC0_BASE_ADDRESS, + VTVC0_BASE_SIZE, + "VTVC0BAR" +}; #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 1e81d7a..c166e3a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -264,14 +264,6 @@ int i; uint32_t mask = 0;
- /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. - */ - m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -311,12 +303,22 @@ * the FSP does not initialize this device */ m_cfg->InternalGfx = 0; + m_cfg->IgdDvmt50PreAlloc = 0; if (config->PrimaryDisplay == Display_iGFX) m_cfg->PrimaryDisplay = Display_Auto; else m_cfg->PrimaryDisplay = config->PrimaryDisplay; } else { m_cfg->InternalGfx = 1; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake + * does not have access to the bios_reserved range so it always + * assumes 8MB is used and so the kernel will avoid the last + * 8MB of the stolen window. With the default stolen size of + * 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel + */ + m_cfg->IgdDvmt50PreAlloc = 2; m_cfg->PrimaryDisplay = config->PrimaryDisplay; } } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00a2782..71a9bee 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,11 +26,12 @@
static void systemagent_vtd_init(void) { - const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); + const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL;
- if (dev) - config = dev->chip_info; + if (root_dev) + config = root_dev->chip_info; if (config && config->ignore_vtd) return;
@@ -39,7 +40,10 @@ if (!vtd_capable) return;
- sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources)); + if (igd_dev && igd_dev->enabled) + sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1); + + sa_set_mch_bar(&soc_vtvc0_mmio_descriptor, 1); }
void systemagent_early_init(void) diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index fa0cd5e..bfaadfd 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -42,6 +42,7 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { + struct device *const igd_dev = SA_DEV_IGD; static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, @@ -56,9 +57,14 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources));
- if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) - sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources, - ARRAY_SIZE(soc_vtd_resources)); + if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) { + if (igd_dev && igd_dev->enabled) + sa_add_fixed_mmio_resources(dev, index, + &soc_gfxvt_mmio_descriptor, 1); + + sa_add_fixed_mmio_resources(dev, index, + &soc_vtvc0_mmio_descriptor, 1); + } }
/*
-
build bot (Jenkins) (Code Review) -
Maxim Polyakov (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)