Change in coreboot[master]: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Nick Vaccaro.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62387 )

Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
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Patch Set 2:

(1 comment)

File util/spd_tools/src/spd_gen/lp5.go:

https://review.coreboot.org/c/coreboot/+/62387/comment/c78b3cbd_3b0bc10f 
PS1, Line 587: if ok == false || tCKMinPs == 0 {
             : 		return LP5GetDefaultTCKMinPs(memAttribs)
             : 	}
> I'm not sure if it makes sense to handle arbitrary speed grades since we've already validated the sp […]

I defined the default speed to TCKMinPs mapping inside the earlier table. Speed validation ensures that the concerned speed is defined in that table. There is still a possibility that someone might forget to add the speedToTCKMinPs map for one or more SoC set. Under that scenario, I have updated the code to log a message and encode TCKMinPs as 0. Hope that addresses your concerns. Please re-open the comment if you are still not convinced.