Change in coreboot[master]: soc/amd: factor out legacy I/O and cf9 decode enable functions
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48435 )
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
soc/amd: factor out legacy I/O and cf9 decode enable functions
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmui_util file to have them all in one place.
Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 24 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48435/1
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..6231d49 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -58,6 +58,21 @@ pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); }
+void fch_enable_cf9_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | CF9_IO_EN); +} + +void fch_enable_legacy_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + +void fch_io_enable_legacy_io(void) +{ + pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 865ad48..0e42ee6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -73,6 +73,9 @@
/* For newer integrated FCHs */ void enable_acpimmio_decode_pm04(void); +void fch_enable_cf9_io(void); +void fch_enable_legacy_io(void); +void fch_io_enable_legacy_io(void);
/* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index b813770..e6c70f6 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -102,11 +102,6 @@ return addr; }
-void sb_enable_legacy_io(void) -{ - pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); -} - static uint32_t map_fch_devices(void) { void *bar; diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index f367dce..8ef2dcd 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -2,6 +2,7 @@
#include "psp_verstage.h"
+#include <amdblocks/acpimmio.h> #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> #include <cbfs.h> @@ -237,7 +238,7 @@ verstage_mainboard_early_init();
svc_write_postcode(POSTCODE_LATE_INIT); - sb_enable_legacy_io(); + fch_io_enable_legacy_io(); verstage_soc_init(); verstage_mainboard_init();
diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index ef5c452..4f85d7c 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -55,6 +55,5 @@ uint32_t verstage_soc_early_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void); -void sb_enable_legacy_io(void);
#endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index bc801a3..3110dea 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -91,20 +91,6 @@ return irq_association; }
-static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -131,8 +117,8 @@ fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); - sb_enable_legacy_io(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); enable_aoac_devices(); sb_reset_i2c_slaves();
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7661607..46fdeb2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -200,20 +200,6 @@ lpc_enable_decode(tmp); }
-static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; @@ -347,14 +333,14 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); + fch_enable_cf9_io(); setup_spread_spectrum(&reboot); setup_misc(&reboot);
if (reboot) warm_reset();
- sb_enable_legacy_io(); + fch_enable_legacy_io(); enable_aoac_devices(); }
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48435 )
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48435/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48435/1//COMMIT_MSG@12 PS1, Line 12: mmui_util mmio_util?
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48435
to look at the new patch set (#2).
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
soc/amd: factor out legacy I/O and cf9 decode enable functions
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place.
Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 24 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48435/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48435 )
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48435/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48435/1//COMMIT_MSG@12 PS1, Line 12: mmui_util
mmio_util?
yep, that was an off-by-one on the keyboard
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48435 )
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48435 )
Change subject: soc/amd: factor out legacy I/O and cf9 decode enable functions ......................................................................
soc/amd: factor out legacy I/O and cf9 decode enable functions
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place.
Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 24 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..6231d49 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -58,6 +58,21 @@ pm_io_write32(ACPIMMIO_DECODE_REGISTER_04, dw); }
+void fch_enable_cf9_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | CF9_IO_EN); +} + +void fch_enable_legacy_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + +void fch_io_enable_legacy_io(void) +{ + pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); +} + /* PM registers are accessed a byte at a time via CD6/CD7 */ uint8_t pm_io_read8(uint8_t reg) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 865ad48..0e42ee6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -73,6 +73,9 @@
/* For newer integrated FCHs */ void enable_acpimmio_decode_pm04(void); +void fch_enable_cf9_io(void); +void fch_enable_legacy_io(void); +void fch_io_enable_legacy_io(void);
/* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index b813770..e6c70f6 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -102,11 +102,6 @@ return addr; }
-void sb_enable_legacy_io(void) -{ - pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); -} - static uint32_t map_fch_devices(void) { void *bar; diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index f367dce..8ef2dcd 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -2,6 +2,7 @@
#include "psp_verstage.h"
+#include <amdblocks/acpimmio.h> #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> #include <cbfs.h> @@ -237,7 +238,7 @@ verstage_mainboard_early_init();
svc_write_postcode(POSTCODE_LATE_INIT); - sb_enable_legacy_io(); + fch_io_enable_legacy_io(); verstage_soc_init(); verstage_mainboard_init();
diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index ef5c452..4f85d7c 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -55,6 +55,5 @@ uint32_t verstage_soc_early_init(void); void verstage_soc_init(void); uintptr_t *map_spi_rom(void); -void sb_enable_legacy_io(void);
#endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index bc801a3..3110dea 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -91,20 +91,6 @@ return irq_association; }
-static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -131,8 +117,8 @@ fch_spi_early_init(); enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); - sb_enable_legacy_io(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); enable_aoac_devices(); sb_reset_i2c_slaves();
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 8815702..ba23e90 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -200,20 +200,6 @@ lpc_enable_decode(tmp); }
-static void sb_enable_cf9_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); -} - -static void sb_enable_legacy_io(void) -{ - uint32_t reg = pm_read32(PM_DECODE_EN); - - pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); -} - void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; @@ -347,14 +333,14 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode_pm04(); fch_smbus_init(); - sb_enable_cf9_io(); + fch_enable_cf9_io(); setup_spread_spectrum(&reboot); setup_misc(&reboot);
if (reboot) warm_reset();
- sb_enable_legacy_io(); + fch_enable_legacy_io(); enable_aoac_devices(); }
-
Felix Held (Code Review) -
Marshall Dawson (Code Review)