[XS] Change in coreboot[main]: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80795?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS
......................................................................

soc/intel/xeon_sp: Drop SPI_BASE_ADDRESS from _CRS

Drop SPI_BASE_ADDRESS since this address is just a regular BAR on
the SPI PCI device. In case the PCI device is hidden in PCI config space
the fast_spi driver will generate the _CRS and thus mark the
SPI_BASE_ADDRESS as reserved.

Thus there's no need to include it unconditionally in the xeon-sp
host bridge for socket 0.

Change-Id: I150397a7ac5d60719f327f6ac6480a38fe295c32
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
3 files changed, 0 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80795/2