Change in coreboot[master]: nb/intel/x4x: Adapt post JEDEC for DDR3

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19918 )

Change subject: nb/intel/x4x: Adapt post JEDEC for DDR3
......................................................................

nb/intel/x4x: Adapt post JEDEC for DDR3

Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/raminit_tables.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 31 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19918/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index fab0df6..b5fcbd8 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -2338,10 +2338,19 @@
    // After JEDEC reset
    MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2;
    FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
-			reg32 = (2 << 18) | (3 << 13) | (5 << 8);
-		else
-			reg32 = (2 << 18) | (3 << 13) | (4 << 8);
+		reg32 = 0;
+		reg32 |= (2 << 18);
+		reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
+			[s->selected_timings.mem_clk][0] << 13;
+		if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&
+			s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz &&
+			ch == 1) {
+			reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk]
+				[s->selected_timings.mem_clk][1] - 1) << 8;
+		} else {
+			reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
+				[s->selected_timings.mem_clk][1] << 8;
+		}
    	MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32;
    	MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80;
    	MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index fabfe18..55ec708 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -247,6 +247,23 @@
    {0x81, 0x00, 0x81, 0x00},	/* 16S_16S */
 };

+const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
+{			/* FSB DDR */
+	{{0x3, 0x5}, /* 800 667 */
+	{0x3, 0x4}, /* 800 800 */
+	},
+	{{0x4, 0x8}, /* 1067 667 */
+	{0x4, 0x6}, /* 1067 800 */
+	{0x3, 0x5}, /* 1067 1066  */
+	},
+	{{0x5, 0x9}, /* 1333 667 */
+	{0x4, 0x7}, /* 1333 800 */
+	{0x4, 0x7}, /* 1333 1066 */
+	{0x4, 0x7} /* 1333 1333 */
+	},
+};
+
+
 const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
    	/* 115h[15:0]	117h[23:0] */
    { /* 1N mode */
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index a243e23..07cc71b 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -379,6 +379,7 @@
 extern const struct dll_setting ddr3_dll_setting_1066[2][23];
 extern const struct dll_setting ddr3_dll_setting_1333[2][23];
 extern const u8 ddr3_emrs1_config[16][4];
+extern const u8 post_jedec_tab[3][4][2];
 extern const u32 ddr3_c2_tab[2][3][6][2];
 extern const u8 ddr3_c2_x264[3][6];
 extern const u16 ddr3_c2_x23c[3][6];