Patch set updated for coreboot: google/gru: Ensure correct pull resistors for special-function pins
Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16711
-gerrit
commit c33e5e974e592639acc07d221328e0e0c7ea43de Author: Julius Werner jwerner@chromium.org Date: Fri Sep 2 11:25:56 2016 -0700
google/gru: Ensure correct pull resistors for special-function pins
Several of the special function pins we're using in firmware have a pre-assigned pull-up or pull-down on power-on reset. We don't want those to interfere with any of the signaling we're trying to do on those pins, so this patch disables them.
Also do some house-cleaning to group the bootblock code better, and change the setup code for all SPI and I2C buses to first initialize the controller and then mux the pins... I assume this might be a little safer (in case the controller peripheral has some pins in a weird state before it gets fully initialized, we don't want to mux it through too early).
BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin.
Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560 Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47 Original-Signed-off-by: Julius Werner jwerner@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/382532 --- src/mainboard/google/gru/bootblock.c | 71 +++++++++++++++++++++++--------- src/mainboard/google/gru/mainboard.c | 37 ++++++++++------- src/mainboard/google/gru/pwm_regulator.c | 5 +++ 3 files changed, 78 insertions(+), 35 deletions(-)
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index c630b2d..d76ec8b 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -63,42 +63,73 @@ void bootblock_mainboard_early_init(void) #endif }
-static void speed_up_boot_cpu(void) +static void configure_spi_flash(void) { - pwm_regulator_configure(PWM_REGULATOR_LIT, 1150); + gpio_input(GPIO(1, A, 7)); /* SPI1_MISO remove pull-up */ + gpio_input(GPIO(1, B, 0)); /* SPI1_MOSI remove pull-up */ + gpio_input(GPIO(1, B, 1)); /* SPI1_CLK remove pull-up */ + gpio_input(GPIO(1, B, 2)); /* SPI1_CS remove pull-up */
- udelay(200); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33*MHz); + rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);
- rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); + write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); + write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); }
-void bootblock_mainboard_init(void) +static void configure_ec(void) { - speed_up_boot_cpu(); - - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); + gpio_input(GPIO(2, C, 4)); /* SPI5_MISO remove pull-up */ + gpio_input(GPIO(2, C, 5)); /* SPI5_MOSI remove pull-up */ + gpio_input(GPIO(2, C, 6)); /* SPI5_CLK remove pull-up */ + gpio_input_pullup(GPIO(2, C, 7)); /* SPI5_CS confirm pull-up */
- /* Set pinmux and configure spi flashrom. */ - write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); - write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); - rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33000*KHz); - rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
- /* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750); +}
+static void configure_tpm(void) +{ if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) { - /* Set pinmux and configure TPM SPI, which is not very fast. */ - write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); + gpio_input(GPIO(3, A, 4)); /* SPI0_MISO remove pull-up */ + gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI remove pull-up */ + gpio_input(GPIO(3, A, 6)); /* SPI0_CLK remove pull-up */ + gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS confirm */ + rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz); + + write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); } else { - /* Set pinmux and configure TPM I2C */ + gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */ + gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */ + + i2c_init(0, 400*KHz); + write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); - i2c_init(0, 400*KHz); } +} + +static void speed_up_boot_cpu(void) +{ + pwm_regulator_configure(PWM_REGULATOR_LIT, 1150); + + udelay(200); + + rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); +} + +void bootblock_mainboard_init(void) +{ + speed_up_boot_cpu(); + + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + + configure_spi_flash(); + configure_ec(); + configure_tpm();
setup_chromeos_gpios(); } diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index a2b74ba..8359ca4 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -94,19 +94,13 @@ static void configure_sdmmc(void)
gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
- /* - * The SD card on this board is connected to port SDMMC0, which is - * multiplexed with GPIO4B pins 0..5. - * - * Disable all pullups on these pins. For pullup configuration - * register layout stacks banks 2 through 4 together, hence [2] means - * group 4, [1] means bank B. This register is described on page 342 - * of section 1 of the TRM. - * - * Each GPIO pin's pull config takes two bits, writing zero to the - * field disables pull ups/downs, as described on page 342 of rk3399 - * TRM Version 0.3 Part 1. - */ + gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */ + gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */ + gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */ + gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */ + gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */ + gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */ + write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
/* @@ -132,6 +126,16 @@ static void configure_sdmmc(void)
static void configure_codec(void) { + gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */ + gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */ + gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */ + gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */ + gpio_input(GPIO(3, D, 4)); /* I2S0_SDI1 remove pull-up */ + /* GPIO3_D5 (I2S0_SDI2SDO2) not connected */ + gpio_input(GPIO(3, D, 6)); /* I2S0_SDO1 remove pull-up */ + gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */ + gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */ + write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0); write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
@@ -206,10 +210,13 @@ static void enable_backlight_booster(void) */ udelay(1000);
- /* Select pinmux for i2c0, which is the display backlight booster. */ + gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */ + gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */ + + i2c_init(0, 100*KHz); + write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); - i2c_init(0, 100*KHz);
for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) { i2c_buf[0] = i2c_writes[i].reg; diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index d6d2eec..a81480a 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -17,6 +17,7 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> +#include <gpio.h> #include <soc/grf.h> #include <soc/pwm.h>
@@ -68,15 +69,19 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt)
switch (pwm) { case PWM_REGULATOR_GPU: + gpio_input(GPIO(4, C, 2)); /* PWM0 remove pull-down */ write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); break; case PWM_REGULATOR_BIG: + gpio_input(GPIO(4, C, 6)); /* PWM1 remove pull-down */ write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); break; case PWM_REGULATOR_LIT: + gpio_input(GPIO(1, C, 3)); /* PWM2 remove pull-down */ write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); break; case PWM_REGULATOR_CENTERLOG: + gpio_input(GPIO(0, A, 6)); /* PWM3 remove pull-down */ write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); break; }
-
Patrick Georgi