Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33801
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
mb/asrock/h110m: set serirq_mode to continuous mode
This option sets the serial IRQ mode for LPC bus in the devicetree.cb
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33801/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..3067ffe 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -62,6 +62,9 @@ register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11"
+ # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02"
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33801 )
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
I don't doubt that it's necessary, but the commit message should state the reason for the change.
https://review.coreboot.org/#/c/33801/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33801/1//COMMIT_MSG@9 PS1, Line 9: This option sets the serial IRQ mode for LPC bus in the devicetree.cb Please mention what it fixes in your case.
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33801
to look at the new patch set (#2).
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
mb/asrock/h110m: set serirq_mode to continuous mode
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port from the SurerIO chip don't work correctly after the LPC controller (PCI 0:1f.0) initialization. Console output is broken. The patch fixes this bug by overriding the serirq_mode options in the devicetree.cb to set Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33801/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33801 )
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33801/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33801/1//COMMIT_MSG@9 PS1, Line 9: This option sets the serial IRQ mode for LPC bus in the devicetree.cb
Please mention what it fixes in your case.
Thanks for comments. I changed it
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33801
to look at the new patch set (#3).
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
mb/asrock/h110m: set serirq_mode to continuous mode
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port from the SurerIO chip don't work correctly after the LPC controller (PCI 0:1f.0) initialization. Console output is broken. The patch fixes this bug by overriding the serirq_mode option in the devicetree.cb to set Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33801/3
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33801 )
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33801 )
Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ......................................................................
mb/asrock/h110m: set serirq_mode to continuous mode
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port from the SurerIO chip don't work correctly after the LPC controller (PCI 0:1f.0) initialization. Console output is broken. The patch fixes this bug by overriding the serirq_mode option in the devicetree.cb to set Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..3067ffe 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -62,6 +62,9 @@ register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11"
+ # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02"
-
Maxim Polyakov (Code Review) -
Nico Huber (Code Review)