[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

[Felix Held (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Sean Rhodes, Subrata Banik.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email )

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Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81080/comment/632c8c80_f0d040ec :
PS3, Line 839: 	if (CONFIG(SOC_ESPI)) {
hmm, looks like SOC_ESPI is defined in the apollolake kconfig, but this is alderlake. also isn't espi being used the default on this newer socs?
would also be good if an Intel engineer could have a look at this patch