Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17820
-gerrit
commit 5849515a97707b664096f71aebdbd10cb7cd4343 Author: Hannah Williams hannah.williams@intel.com Date: Wed Oct 26 15:30:48 2016 -0700
mainboard/glkrvp: devicetree.cb for GLKRVP
Change-Id: I3ec1eadab507bb0f938e71a6404f53995ba0b908 Signed-off-by: Hannah Williams hannah.williams@intel.com --- .../intel/glkrvp/variants/baseboard/devicetree.cb | 44 +++++++++++++--------- 1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index e9cd995..5322323 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -4,12 +4,12 @@ chip soc/intel/glk device lapic 0 on end end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports - register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp1_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "1" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
# GPIO for PERST_0 @@ -78,33 +78,37 @@ chip soc/intel/glk device pci 00.2 on end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Iunit + device pci 0c.0 on end # - CNVi device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on end # - Audio + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - Heci1 + device pci 0f.1 on end # - Heci2 + device pci 0f.2 on end # - Heci3 device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - PCIe-A 0 + device pci 12.0 on end # - SATA + device pci 13.0 off end # - PCIe-A 0 Slot 1 device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 off end # - PCIe-A 2 + device pci 13.2 on end # - PCIe-A 2 Onboard Lan device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 off end # - PCIe-B 0 - device pci 14.1 off end # - PCIe-B 1 + device pci 14.0 off end # - PCIe-B 0 Slot2 + device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT) device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 - device pci 16.3 on end # - I2C 3 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 + device pci 18.1 off end # - UART 1 device pci 18.2 on end # - UART 2 - device pci 18.3 on end # - UART 3 + device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 device pci 19.1 on end # - SPI 1 device pci 19.2 on end # - SPI 2 @@ -113,6 +117,12 @@ chip soc/intel/glk device pci 1c.0 on end # - eMMC device pci 1e.0 off end # - SDIO device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end chip ec/google/chromeec device pnp 0c09.0 on end end
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Hannah Williams