Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change some gpio settings ......................................................................
mb/google/volteer: change some gpio settings
This CL changes some GPIO settings.
BUG=b:144933687, b:148179954 BRANCH=none TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/39337/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3f1f2b0..a00d960 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ PAD_CFG_GPI(GPP_A9, NONE, DEEP), /* A10 : I2S2_RXD ==> EN_SPKR_PA */ PAD_CFG_GPO(GPP_A10, 1, DEEP), - /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), @@ -146,7 +146,7 @@ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE), + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ @@ -381,7 +381,7 @@ /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_GPI(GPD2, NONE, DEEP), + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change some gpio settings ......................................................................
Patch Set 1: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change some gpio settings ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG@7 PS1, Line 7: some two
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG@9 PS1, Line 9: This CL changes some GPIO settings. Please be more specific.
Hello build bot (Jenkins), Furquan Shaikh, caveh jalali, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39337
to look at the new patch set (#2).
Change subject: mb/google/volteer: change two gpio settings ......................................................................
mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954 BRANCH=none TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/39337/2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG@7 PS1, Line 7: some
two
Done
https://review.coreboot.org/c/coreboot/+/39337/1//COMMIT_MSG@9 PS1, Line 9: This CL changes some GPIO settings.
Please be more specific.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... PS1, Line 149: PAD_CFG_GPI_INT Why is this GPI_INT? Why is it not using APIC?
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... PS1, Line 149: PAD_CFG_GPI_INT
Why is this GPI_INT? Why is it not using APIC?
I was bringing these changes over as-is from private repo. It was initially changed here: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb...
Should it be APIC? Review owner said code was verified functional.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... PS1, Line 149: PAD_CFG_GPI_INT
I was bringing these changes over as-is from private repo. It was initially changed here: […]
Just checked the original bug. It looks like we have an APIC interrupt conflict and so we went with GPI_INT.
It would be good to add a comment here indicating that. Also, reminds me.. we need to fix the IRQ configuration CL in SoC.
Hello build bot (Jenkins), Furquan Shaikh, caveh jalali, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39337
to look at the new patch set (#3).
Change subject: mb/google/volteer: change two gpio settings ......................................................................
mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954 BRANCH=none TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/39337/3
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39337/1/src/mainboard/google/voltee... PS1, Line 149: PAD_CFG_GPI_INT
Just checked the original bug. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
mb/google/volteer: change two gpio settings
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954 BRANCH=none TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3f1f2b0..f6dbed0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ PAD_CFG_GPI(GPP_A9, NONE, DEEP), /* A10 : I2S2_RXD ==> EN_SPKR_PA */ PAD_CFG_GPO(GPP_A10, 1, DEEP), - /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), @@ -146,7 +146,8 @@ /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE), + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ @@ -381,7 +382,7 @@ /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ - PAD_CFG_GPI(GPD2, NONE, DEEP), + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39337 )
Change subject: mb/google/volteer: change two gpio settings ......................................................................
Patch Set 3: Code-Review+1
please add topic TGL_UPSTREAM.