Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52868 )
Change subject: mb/google/guybrush: Update power-on timings for PCIe devices ......................................................................
mb/google/guybrush: Update power-on timings for PCIe devices
This configures the PCIe GPIOs in the correct sequence to meet the power-on timings.
WLAN_AUX_RESET is active-high, and the FSP currently only works with active-low reset lines.
BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training.
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 --- M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/guybrush/bootblock.c M src/mainboard/google/guybrush/port_descriptors.c A src/mainboard/google/guybrush/romstage.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h 7 files changed, 86 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52868/1
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index d4eeaf5..ecd031a 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -11,6 +11,7 @@ endif
romstage-y += port_descriptors.c +romstage-y += romstage.c
ramstage-y += mainboard.c ramstage-y += ec.c diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 5b18d37..46240bc 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -38,3 +38,15 @@ if (variant_has_fpmcu()) variant_fpmcu_reset(); } + +void bootblock_mainboard_init(void){ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + /* + * Set GPIOs to bring up power for WWAN & WLAN. This needs to happen + * at the end of bootblock to meet timing requirements. + */ + gpios = variant_bootblock_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index cc1fa1a..78801bd 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -15,7 +15,6 @@ .function_number = 1, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .gpio_group_id = GPIO_29, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* SD */ diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c new file mode 100644 index 0000000..6b3448f --- /dev/null +++ b/src/mainboard/google/guybrush/romstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fsp/api.h> + +void mb_pre_fspm_init(void) +{ + /* + * Initialize the AUX PCIe reset lines to meet the power-on + * timings. + */ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_pcie_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc index 88aa1a4..c8d007d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += helpers.c
romstage-y += tpm_tis.c +romstage-y += gpio.c
ramstage-y += gpio.c ramstage-y += tpm_tis.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 528ace1..a33ed24 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -7,6 +7,7 @@ #include <soc/gpio.h>
/* GPIO configuration in ramstage*/ +/* Please make sure that *ALL* GPIOs are configured in this table */ static const struct soc_amd_gpio base_gpio_table[] = { /* PWR_BTN_L */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), @@ -40,7 +41,7 @@ /* SOC_SAR_INT_L */ PAD_INT(GPIO_17, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* WWAN_AUX_RESET_L */ - PAD_GPO(GPIO_18, LOW), + PAD_GPO(GPIO_18, HIGH), /* I2C3_SCL */ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ @@ -60,7 +61,7 @@ /* PCIE_RST1_L */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ - /* WLAN_AUX_RESET */ + /* WLAN_AUX_RESET (Active HIGH)*/ PAD_GPO(GPIO_29, LOW), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), @@ -171,10 +172,7 @@ PAD_GPO(GPIO_6, HIGH), /* EN_PWR_WWAN_X */ PAD_GPO(GPIO_8, HIGH), - /* WWAN_DISABLE */ - PAD_GPO(GPIO_85, LOW), - /* WLAN_DISABLE */ - PAD_GPO(GPIO_130, LOW), + /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* I2C3_SCL */ @@ -203,11 +201,55 @@ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), };
+/* + * For the correct power sequencing, there's a minimum of 20ms between Early + * GPIO configuration and bootblock_gpio_table. Currently there's about 23ms + * between the two calls. The first call is within 1ms of the start of bootblock + * and will be moved to psp_verstage when that starts running. The bootblock + * GPIO initialization happens roughly 3.5ms before the end of bootblock. + */ +static const struct soc_amd_gpio bootblock_gpio_table[] = { + /* WWAN_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* WLAN_DISABLE */ + PAD_GPO(GPIO_130, LOW), +}; + /* GPIO configuration for sleep */ static const struct soc_amd_gpio sleep_gpio_table[] = { /* TODO: Fill sleep gpio configuration */ };
+/* + * The pcie_gpio configuration needs to happen at least 30ms after the + * bootblock_gpio_table initialization and 100ms after the early_gpio_table + * call. Even after verstage is moved to the PSP, this will still happen + * roughly 120ms after bootblock. This includes the time to load romstage + * and FSP-M. + */ +static const struct soc_amd_gpio pcie_gpio_table[] = { + /* WWAN_AUX_RESET_L */ + PAD_GPO(GPIO_18, HIGH), + /* WLAN_AUX_RESET (ACTIVE HIGH) */ + PAD_GPO(GPIO_29, LOW), + /* SSD_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_70, HIGH), +}; + +const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(pcie_gpio_table); + return pcie_gpio_table; +} + +const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(bootblock_gpio_table); + return bootblock_gpio_table; +} + const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size) { *size = ARRAY_SIZE(base_gpio_table); diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 5fb7462..a80d38e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -18,9 +18,15 @@ */ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
-/* This function provides early GPIO init in bootblock or psp. */ +/* This function provides early GPIO init in early bootblock or psp. */ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
+/* This function provides GPIO settings at the end of bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size); + +/* This function provides GPIO settings before PCIe enumeration. */ +const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); + /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);