Change in coreboot[master]: [WIP]soc/amd/cezanne: Add an function to select eSPI channel

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/50187

to review the following change.

Change subject: [WIP]soc/amd/cezanne: Add an function to select eSPI channel
......................................................................

[WIP]soc/amd/cezanne: Add an function to select eSPI channel

Cezanne got two eSPI channels. eSPI0 shares pins with SPI.
eSPI1 shares with LPC. To select the channel, the IOMUX registers
about these pins are needed to be set.

Change-Id: Ic110971051a25ab129608b80f8bd3395397e74ae
Signed-off-by: Zheng Bao 
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
2 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50187/1

diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index dd096e0..6ab91c6 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -1,13 +1,56 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <device/pci_ops.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/espi.h>
 #include <amdblocks/lpc.h>
 #include <amdblocks/smbus.h>
 #include <console/console.h>
+#include <soc/pci_devs.h>
 #include <soc/southbridge.h>
+#include <soc/gpio.h>
 #include <soc/uart.h>

+void fch_espi_channel_sel(uint8_t channel)
+{
+	uint32_t dword;
+	uint8_t byte;
+
+	struct soc_amd_gpio espi_mux_chan0[] = {
+		PAD_NF(GPIO_86,  LPC_SMI_L, PULL_NONE),
+		PAD_NF(GPIO_104, LAD0, PULL_NONE),
+		PAD_NF(GPIO_105, LAD1, PULL_NONE),
+		PAD_NF(GPIO_106, LAD2, PULL_NONE),
+		PAD_NF(GPIO_107, LAD3, PULL_NONE),
+		PAD_NF(GPIO_108, LDRQ0_L, PULL_NONE),
+	};
+
+	struct soc_amd_gpio espi_mux_chan1[] = {
+		PAD_NF (GPIO_30, ESPI_CS_L, PULL_NONE),
+		PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
+		PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
+		PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
+		PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
+		PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
+	};
+
+	if (channel == 0) {
+		program_gpios(espi_mux_chan0, ARRAY_SIZE(espi_mux_chan0));
+		byte = pm_read8(0x92);
+		byte &= ~1;
+		pm_write8(0x92, byte);
+		dword = pm_read32(0x74);
+		dword &= ~(3 << 10);
+		pm_write32(0x74, dword);
+	} else {
+		program_gpios(espi_mux_chan1, ARRAY_SIZE(espi_mux_chan1));
+		/* Dedicate alert pin */
+		dword = pci_read_config32(SOC_LPC_DEV, 0x74);
+		dword &= ~(3 << 2 | 3 << 9);
+		dword |= 1 << 9;
+		pci_write_config32(SOC_LPC_DEV, 0x74, dword);
+	}
+}
 /* Before console init */
 void fch_pre_init(void)
 {
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index d57fbfe..c9b9aaa 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -56,4 +56,6 @@
 void enable_aoac_devices(void);
 void wait_for_aoac_enabled(unsigned int dev);

+void fch_espi_channel_sel(unsigned char channel);
+
 #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */