[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Expend EC share memory register defi...

[EricKY Cheng (Code Review)]

Attention is currently required from: Tim Wawrzynczak.

EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68077 )

Change subject: mb/google/skyrim/var/winterhold: Expend EC share memory register define for Dynamic Thermal Table Switching Proposal.
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mb/google/skyrim/var/winterhold: Expend EC share memory register define
for Dynamic Thermal Table Switching Proposal.

Define offset 0x09 bit 5 for temperature status of thermal table switch
Define offset 0x09 bit 6 for body detection status of thermal table switch

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng 
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/1

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 70bb18d..0a73dd5 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -56,6 +56,9 @@
    	CHGL, 8,	// Charger Current Limit
    	TBMD, 1,	// Tablet mode
    	DDPN, 3,	// Device DPTF Profile Number
+		RSV1, 1,	// Reserved bit
+		STTT, 1,	// Switch thermal table by temperature status
+		STTB, 1,    // Switch thermal table by body detection status
    	// DFUD must be 0 for the other 31 values to be valid
    	Offset (0x0a),
    	DFUD, 1,	// Device Features Undefined