Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Meera Ravindranath (Code Review)]

Attention is currently required from: Bora Guvendik, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Meera Ravindranath.
Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50996

to look at the new patch set (#12).

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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mb/adlrvp: Fix DDR5 Boot issue

The coreboot SMBus driver requires additional changes
to accomodate the DDR5 EEPROM read which has resulted in a
broken code flow for boot.

This CL serves as a temp WA to let FSP perform the SPD read
for DDR5 and pass SPD addresses to FSP UPD array.

BUG=b:180458099
TEST=Build and boot DDR5 adlrvp to OS

Signed-off-by: Meera Ravindranath 
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/12