Change in ...coreboot[master]: nb/intel/i945: Put stage cache in TSEG

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25603 )

Change subject: nb/intel/i945: Put stage cache in TSEG
......................................................................

nb/intel/i945: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Tested on Intel D945GCLF and Lenovo Thinkpad X60, on cold boot the
external stage cache gets created and the stage cache gets properly
used on S3 resume.

Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/25603
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
A src/northbridge/intel/i945/stage_cache.c
3 files changed, 41 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, but someone else must approve
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 996e1d9..2c21420 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -31,6 +31,7 @@
    select POSTCAR_CONSOLE
    select SMM_TSEG
    select PARALLEL_MP
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
    def_bool n
@@ -90,4 +91,8 @@
      On other boards the check always creates a false positive,
      effectively making it impossible to resume.

+config SMM_RESERVED_SIZE
+	hex
+	default 0x100000
+
 endif
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index ffeabdc..47014bc 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -31,4 +31,8 @@

postcar-y += ram_calc.c

+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+
 endif
diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c
new file mode 100644
index 0000000..26d4e7e
--- /dev/null
+++ b/src/northbridge/intel/i945/stage_cache.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <stage_cache.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include "i945.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/*
+	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+	 * The top of RAM is defined to be the TSEG base address.
+	 */
+	*size = CONFIG_SMM_RESERVED_SIZE;
+	*base = (void *)(northbridge_get_tseg_base()
+			 + CONFIG_SMM_RESERVED_SIZE);
+}