Change in coreboot[master]: mb/google/dedede: Enable SaGv support

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45196 )

Change subject: mb/google/dedede: Enable SaGv support
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mb/google/dedede: Enable SaGv support

Allow MRC training in SaGv low, mid and high frequencies.

TEST=Verify memory trains at low, mid and high SaGv point
     through FSP debug logs enabled.

Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196
Reviewed-by: Angel Pons 
Reviewed-by: Karthik Ramasubramanian 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index fe232e6..b2ed21a 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -168,6 +168,9 @@
    # Skip the CPU repalcement check
    register "SkipCpuReplacementCheck" = "1"

+	# Sagv Configuration
+	register "SaGv" = "SaGv_Enabled"
+
    # Set the minimum assertion width
    register "PchPmSlpS3MinAssert"  = "3"  # 50ms
    register "PchPmSlpS4MinAssert"  = "1"  # 1s