Change in coreboot[master]: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21.
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40917/1
diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 94af1b6..b53b2b3 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,8 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
+#include <arch/mmio.h> #include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void*) m_cfg; + + // BoardId + write8(start + 140, 0x1d); + + // BoardTypeBitmask + write32(start + 104, 0x11111111); + + // DebugPrintLevel + write8(start + 45, 8); + + // KtiLinkSpeedMode + write8(start + 64, 0); + + // KtiPrefetchEn + write8(start + 53, 2); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40917/1/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/romstage.c:
https://review.coreboot.org/c/coreboot/+/40917/1/src/mainboard/intel/cedaris... PS1, Line 10: void *start = (void*) m_cfg; "(foo*)" should be "(foo *)"
Andrey Petrov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21.
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40917/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/romstage.c:
https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... PS2, Line 13: write8(start + 140, 0x1d); That's an interesting way of setting FSP parameters. Any reason as to why it's being done this way?
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/romstage.c:
https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... PS2, Line 13: write8(start + 140, 0x1d);
That's an interesting way of setting FSP parameters. […]
this is because Intel did not release the headers for public consumption yet and the headers we now have in the tree are dummies. Once proper headers land in the tree this will have to be rewritten with proper structure->field references.
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40917 )
Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M ......................................................................
mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21.
Signed-off-by: Andrey Petrov anpetrov@fb.com Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/cedarisland_crb/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved
diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 94af1b6..0d1ccab 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,8 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
+#include <arch/mmio.h> #include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void *) m_cfg; + + // BoardId + write8(start + 140, 0x1d); + + // BoardTypeBitmask + write32(start + 104, 0x11111111); + + // DebugPrintLevel + write8(start + 45, 8); + + // KtiLinkSpeedMode + write8(start + 64, 0); + + // KtiPrefetchEn + write8(start + 53, 2); }
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Andrey Petrov (Code Review) -
Angel Pons (Code Review)
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build bot (Jenkins) (Code Review)
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Maxim Polyakov (Code Review)