Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )

Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/38998/9/src/mainboard/intel/tglrvp/... 
PS9, Line 84: 		mem_cfg->SpdAddressTable[0] = 0x0;
> Based on the comment in the Fspm header file we are setting it to 0 when MemorySpdPtr is used.

I believe this UPD already defaults to 0. If you still want to ensure that this doesn't change going forward, you can add this in meminit_lpddr4x_dimm0() itself so that all mainboards can take advantage of that.