Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges - coreboot-gerrit

2 May 2022


      Attention is currently required from: Mario Scheithauer.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridges
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Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/d58a216b_c137e9a8 
PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
There is just one bridge on this board.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Gerrit-Change-Number: 63931
Gerrit-PatchSet: 2
Gerrit-Owner: Mario Scheithauer mario.scheithauer@siemens.com
Gerrit-Reviewer: Werner Zeh werner.zeh@siemens.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Mario Scheithauer mario.scheithauer@siemens.com
Gerrit-Comment-Date: Mon, 02 May 2022 06:26:42 +0000
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