Change in coreboot[master]: soc/intel/alderlake: support for PCIe slot & device detect timeout

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jeremy Compostella, Subrata Banik, Tim Wawrzynczak.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63942 )

Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
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Patch Set 7:

(2 comments)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/63942/comment/c683b338_8904cb50 
PS6, Line 671: 		if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
> double negation is unnecessary in a if statement. […]

double negation has been used in several places. also, in if-conditions. if-condition is used here only update when different from FSP default.

File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:

https://review.coreboot.org/c/coreboot/+/63942/comment/8dc5b8bd_45f078dd 
PS6, Line 30: 	/* indicates that this root port is built-in */
> missing ending dot character.

Done