build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27875 )
Change subject: src: Fix typo ......................................................................
Patch Set 2:
(40 comments)
https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/time... File src/commonlib/include/commonlib/timestamp_serialized.h:
https://review.coreboot.org/#/c/27875/2/src/commonlib/include/commonlib/time... PS2, Line 243: { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/resou... File src/mainboard/advansus/a785e-i/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/advansus/a785e-i/resou... PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/resou... File src/mainboard/amd/bimini_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/bimini_fam10/resou... PS2, Line 123: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/res... File src/mainboard/amd/mahogany_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/mahogany_fam10/res... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah_... File src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/serengeti_cheetah_... PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/main... File src/mainboard/amd/south_station/mainboard.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/south_station/main... PS2, Line 21: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/reso... File src/mainboard/amd/tilapia_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/tilapia_fam10/reso... PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h File src/mainboard/amd/torpedo/gpio.h:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@301 PS2, Line 301: #define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/torpedo/gpio.h@302 PS2, Line 302: #define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/main... File src/mainboard/amd/union_station/mainboard.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/amd/union_station/main... PS2, Line 20: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcem... File src/mainboard/asus/kcma-d8/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcem... PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kcma-d8/resourcem... PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resourc... File src/mainboard/asus/kfsn4-dre/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kfsn4-dre/resourc... PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resource... File src/mainboard/asus/kgpe-d16/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resource... PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/kgpe-d16/resource... PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resource... File src/mainboard/asus/m4a78-em/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a78-em/resource... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resource... File src/mainboard/asus/m4a785-m/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m4a785-m/resource... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resourcem... File src/mainboard/asus/m5a88-v/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/asus/m5a88-v/resourcem... PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resour... File src/mainboard/avalue/eax-785e/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/avalue/eax-785e/resour... PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/resou... File src/mainboard/gigabyte/ma785gm/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gm/resou... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/reso... File src/mainboard/gigabyte/ma785gmt/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma785gmt/reso... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resour... File src/mainboard/gigabyte/ma78gm/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/gigabyte/ma78gm/resour... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10/... File src/mainboard/iei/kino-780am2-fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/iei/kino-780am2-fam10/... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resourc... File src/mainboard/jetway/pa78vm5/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/jetway/pa78vm5/resourc... PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/resou... File src/mainboard/msi/ms9652_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/msi/ms9652_fam10/resou... PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn346... File src/mainboard/siemens/mc_tcu3/ptn3460.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn346... PS2, Line 117: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn346... PS2, Line 143: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/siemens/mc_tcu3/ptn346... PS2, Line 171: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam10... File src/mainboard/supermicro/h8dmr_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8dmr_fam10... PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam10... File src/mainboard/supermicro/h8qme_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8qme_fam10... PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam10... File src/mainboard/supermicro/h8scm_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/supermicro/h8scm_fam10... PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/resou... File src/mainboard/tyan/s2912_fam10/resourcemap.c:
https://review.coreboot.org/#/c/27875/2/src/mainboard/tyan/s2912_fam10/resou... PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam1... File src/northbridge/amd/amdfam10/amdfam10.h:
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam1... PS2, Line 371: for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam1... PS2, Line 372: for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdfam10/amdfam1... PS2, Line 373: F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h File src/northbridge/amd/amdht/h3ffeat.h:
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ffeat.h@... PS2, Line 160: /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c:
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdht/h3ncmn.c@1... PS2, Line 1119: * InitComplete = 1,Link initialization is complete line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/mct_ddr3/... PS2, Line 849: /* Restore DRAM Address/Timing Control Register */ line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers/... File src/northbridge/amd/amdmct/wrappers/mcti_d.c:
https://review.coreboot.org/#/c/27875/2/src/northbridge/amd/amdmct/wrappers/... PS2, Line 172: //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ line over 80 characters
https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_ear... File src/superio/smsc/sio1036/sio1036_early_init.c:
https://review.coreboot.org/#/c/27875/2/src/superio/smsc/sio1036/sio1036_ear... PS2, Line 76: pnp_write_config (dev, 0x0A, 0x00 | IR_OUTPUT_MUX); space prohibited between function name and open parenthesis '('
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