Change in coreboot[master]: soc/intel/alderlake: [TEST] Disable CPU PCIe FIA programming

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61597 )

Change subject: soc/intel/alderlake: [TEST] Disable CPU PCIe FIA programming
......................................................................

soc/intel/alderlake: [TEST] Disable CPU PCIe FIA programming

Signed-off-by: Sridhar Siricilla 
Change-Id: Ic41a45b734fea6d8c7c47f2d9e06daee8556ac2d
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/61597/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index ffcaa73..1c82579 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -633,6 +633,9 @@
    	s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
    	s_cfg->PtmEnabled[i] = 0;
    }
+
+	/* Disable CPU PCIe FIA programming */
+	s_cfg->CpuPcieFiaProgramming = 0;
 }

static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,