Change in coreboot[master]: soc/intel/skylake: Restore alphabetical order of Kconfig selects

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48376 )

Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects
......................................................................

soc/intel/skylake: Restore alphabetical order of Kconfig selects

Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13
Signed-off-by: Felix Singer 
---
M src/soc/intel/skylake/Kconfig
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48376/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 314a08b..3eae5f8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -30,20 +30,20 @@
    select GENERIC_GPIO_LIB
    select HAVE_FSP_GOP
    select HAVE_FSP_LOGO_SUPPORT
-	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select HAVE_INTEL_FSP_REPO
    select HAVE_SMI_HANDLER
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select HAVE_INTEL_FSP_REPO
    select IOAPIC
    select MRC_SETTINGS_PROTECT
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
-	select REG_SCRIPT
-	select SA_ENABLE_DPR
    select PM_ACPI_TIMER_OPTIONAL
    select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select REG_SCRIPT
+	select SA_ENABLE_DPR
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48376 )

Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects
......................................................................

Patch Set 1: Code-Review+1

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48376 )

Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects
......................................................................

Patch Set 2: Code-Review+2

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48376 )

Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects
......................................................................

Patch Set 3: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48376 )

Change subject: soc/intel/skylake: Restore alphabetical order of Kconfig selects
......................................................................

soc/intel/skylake: Restore alphabetical order of Kconfig selects

Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376
Reviewed-by: Frans Hendriks 
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/Kconfig
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Frans Hendriks: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 314a08b..3eae5f8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -30,20 +30,20 @@
    select GENERIC_GPIO_LIB
    select HAVE_FSP_GOP
    select HAVE_FSP_LOGO_SUPPORT
-	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select HAVE_INTEL_FSP_REPO
    select HAVE_SMI_HANDLER
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select HAVE_INTEL_FSP_REPO
    select IOAPIC
    select MRC_SETTINGS_PROTECT
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
-	select REG_SCRIPT
-	select SA_ENABLE_DPR
    select PM_ACPI_TIMER_OPTIONAL
    select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select REG_SCRIPT
+	select SA_ENABLE_DPR
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK