Change in coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formating

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29428

Change subject: sb/intel/bd82x6x/early_usb.c: Fix formating
......................................................................

sb/intel/bd82x6x/early_usb.c: Fix formating

Remove whitespace between the function name and open
parenthesis, and fix 81+ characters lines.

Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/bd82x6x/early_usb.c
1 file changed, 12 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29428/1

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index d4ff783..527c93f 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -20,8 +20,7 @@
 #include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE.  */
 #include "pch.h"

-void
-early_usb_init (const struct southbridge_usb_port *portmap)
+void early_usb_init(const struct southbridge_usb_port *portmap)
 {
    u32 reg32;
    const u32 rcba_dump[8] = {
@@ -35,41 +34,42 @@
    /* Activate PMBAR.  */
    pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
    pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
+	/* Enable ACPI BAR */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);

/* Unlock registers.  */
    outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,
         DEFAULT_PMBASE | UPRWC);

for (i = 0; i < 14; i++)
-		write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
+		write32(DEFAULT_RCBABASE + (0x3500 + 4 * i),
    		 currents[portmap[i].current]);
    for (i = 0; i < 10; i++)
-		write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
+		write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);

for (i = 0; i < 8; i++)
-		write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
+		write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
    for (i = 0; i < 8; i++)
-		write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
+		write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
    reg32 = 0;
    for (i = 0; i < 14; i++)
    	if (!portmap[i].enabled)
    		reg32 |= (1 << i);
-	write32 (DEFAULT_RCBABASE + USBPDO, reg32);
+	write32(DEFAULT_RCBABASE + USBPDO, reg32);
    reg32 = 0;
    for (i = 0; i < 8; i++)
    	if (portmap[i].enabled && portmap[i].oc_pin >= 0)
    		reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
-	write32 (DEFAULT_RCBABASE + USBOCM1, reg32);
+	write32(DEFAULT_RCBABASE + USBOCM1, reg32);
    reg32 = 0;
    for (i = 8; i < 14; i++)
    	if (portmap[i].enabled && portmap[i].oc_pin >= 4)
    		reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
-	write32 (DEFAULT_RCBABASE + USBOCM2, reg32);
+	write32(DEFAULT_RCBABASE + USBOCM2, reg32);
    for (i = 0; i < 22; i++)
-		write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
+		write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);

-	pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+	pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000);

/* Relock registers.  */
    outw(0, DEFAULT_PMBASE | UPRWC);