Change in coreboot[master]: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39988 )
Change subject: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting ......................................................................
mb/intel/icelake_rvp/variants/icl_u: Improve code formatting
Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/39988/1
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 12acced..40f17ce 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -169,10 +169,10 @@ #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | #| | for TPM communication | - #| | before memory is up | + #| | before memory is up | #+-------------------+---------------------------+
register "common_soc_config" = "{ @@ -186,8 +186,8 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -295,8 +295,8 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -337,7 +337,7 @@ device spi 0 on end end end # GSPI #1 - device pci 1f.0 on end # eSPI Interface + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39988 )
Change subject: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39988 )
Change subject: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39988 )
Change subject: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting ......................................................................
mb/intel/icelake_rvp/variants/icl_u: Improve code formatting
Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb 1 file changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 12acced..40f17ce 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -169,10 +169,10 @@ #| Field | Value | #+-------------------+---------------------------+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI1 | cr50 TPM. Early init is | - #| | required to set up a BAR | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | #| | for TPM communication | - #| | before memory is up | + #| | before memory is up | #+-------------------+---------------------------+
register "common_soc_config" = "{ @@ -186,8 +186,8 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -295,8 +295,8 @@ end end # I2C 0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -337,7 +337,7 @@ device spi 0 on end end end # GSPI #1 - device pci 1f.0 on end # eSPI Interface + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39988 )
Change subject: mb/intel/icelake_rvp/variants/icl_u: Improve code formatting ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2219 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2218 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2217
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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HAOUAS Elyes (Code Review)
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Paul Menzel (Code Review)