Change in coreboot[master]: soc/intel/tigerlake: Refactor TCSS port mux config - coreboot-gerrit

23 Nov 2020


      Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47860 )
Change subject: soc/intel/tigerlake: Refactor TCSS port mux config
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Patch Set 1:
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Patch Set 1:
also another suggestion, could be another patch, this is already so much better than just raw constants, but would be nice to just specify GPP_A10 for example in the bias_control fields; that would mean decoding the bank and pin numbers though.
ya, i was looking for a way to decode the pin numbers. is that done on the FSP side?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0ca69cba646e3dcb7dc73e5d95aedc88fcde0e81
Gerrit-Change-Number: 47860
Gerrit-PatchSet: 1
Gerrit-Owner: Caveh Jalali caveh@chromium.org
Gerrit-Reviewer: Brandon Breitenstein brandon.breitenstein@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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Gerrit-Comment-Date: Mon, 23 Nov 2020 20:22:09 +0000
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