[XS] Change in coreboot[main]: mb/google/brya/vell: Enable RTD3 for SSD

[Pranava Y N (Code Review)]

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86646?usp=email )

Change subject: mb/google/brya/vell: Enable RTD3 for SSD
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mb/google/brya/vell: Enable RTD3 for SSD

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on vell and verify that the device
suspends to S0ix.

Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/vell/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/86646/1

diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 697d0ef..6f9b325 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -191,6 +191,13 @@
    			.clk_src = 1,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
    	end
    	device ref tbt_pcie_rp3 on end
    	device ref cnvi_wifi on