Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21111
Change subject: nb/amd/amdk8: Link early_ht.c ......................................................................
nb/amd/amdk8: Link early_ht.c
Change-Id: Ia47f2466c8d6583a9bb668cc35e91f45765c8238 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/early_ht.c 32 files changed, 9 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21111/1
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index c8c8c40..4146197 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -51,7 +51,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index a723ee7..960df43 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -54,7 +54,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 052b71f..4e9c6ad 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -47,7 +47,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 21324e7..9607394 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -57,7 +57,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_init(void) { diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 20c57c1..44c080e 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -57,7 +57,6 @@ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 88a05f4..5d9856b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3628d07..c9e9552 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 83bf27b..de55231 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index f646c2b..d287bd6 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -59,7 +59,6 @@ #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
#define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 88b817d..e298c10 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -69,7 +69,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
/* FIXME * Dummy method to allow build diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index d4cf882..cc42f0e 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -44,7 +44,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 (6 << 8) #define RC1 (7 << 8) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index d56de52..f7871cb 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -74,7 +74,6 @@ #include <southbridge/sis/sis966/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 0acb9c2..428fa9d 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -75,7 +75,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index ce9d5ac..9fa5418 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -70,7 +70,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
#if 0 #include "ipmi.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index ae5970e..89e998e 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -52,7 +52,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 7d8007c..3ba1a90 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -60,7 +60,6 @@ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void ms7135_set_ram_voltage(void) { diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 3402b81..b7aaa6d 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -78,7 +78,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 33dc288..23f0275 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -69,7 +69,6 @@ #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 (0x10 << 8) #define RC1 (0x01 << 8) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index f8e7e4b..ed4aecc 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -85,7 +85,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
/* FIXME * Dummy method to allow build diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index a1665f8..c2c8049 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index dec5c68..692e7dc 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -67,7 +67,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
#define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) #define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 8a9d81e..b0b02c3 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -63,7 +63,6 @@
#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 589cee1..275c6cc 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -74,7 +74,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index edf717c..453a2d2 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 9cd3311..f00f996 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -69,7 +69,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 520247e..84b52cd 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -54,7 +54,6 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "tn_post_code.c" #include "speaker.c" -#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 1bb4a7f..01a0a11 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -53,7 +53,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index fb89141..d15732a 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index ac4c3b4..fd4ae5f 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -40,7 +40,6 @@ #if IS_ENABLED(CONFIG_SET_FIDVID) #include "cpu/amd/model_fxx/fidvid.c" #endif -#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) { diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 77bf375..ed55a7e 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += reset_test.c romstage-y += coherent_ht.c romstage-y += setup_resource_map.c +romstage-y += early_ht.c
# Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdk8.h is included. diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index b183976..63c4e47 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -33,6 +33,7 @@ void setup_resource_map_x_offset(const unsigned int *register_values, int max, unsigned int offset_pci_dev, unsigned int offset_io_base); +void enumerate_ht_chain(void);
#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void setup_coherent_ht_domain(void); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 638511a..269bb77 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -2,7 +2,13 @@ 2005.11 yhlu add let the real sb to use small unitid */ // only for sb ht chain -static void enumerate_ht_chain(void) + +#include <arch/io.h> +#include <console/console.h> + +#include "amdk8.h" + +void enumerate_ht_chain(void) { #if CONFIG_HT_CHAIN_UNITID_BASE != 0 /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */
-
Arthur Heymans (Code Review)