Change in coreboot[master]: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability - coreboot-gerrit

6 Jul 2021


      Attention is currently required from: Hung-Te Lin, Ryan Chuang, Yu-Ping Wu.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56105 )
Change subject: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56105/comment/cf597f13_10e46755 
PS2, Line 7: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for enter/exit S0 stability
...
Line too long
Done
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/56105
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707
Gerrit-Change-Number: 56105
Gerrit-PatchSet: 3
Gerrit-Owner: Rex-BC Chen rex-bc.chen@mediatek.corp-partner.google.com
Gerrit-Reviewer: Hung-Te Lin hungte@chromium.org
Gerrit-Reviewer: Ryan Chuang ryan.chuang@mediatek.corp-partner.google.com
Gerrit-Reviewer: Yu-Ping Wu yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Paul Menzel paulepanter@mailbox.org
Gerrit-Attention: Hung-Te Lin hungte@chromium.org
Gerrit-Attention: Ryan Chuang ryan.chuang@mediatek.corp-partner.google.com
Gerrit-Attention: Yu-Ping Wu yupingso@google.com
Gerrit-Comment-Date: Tue, 06 Jul 2021 10:21:28 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Yu-Ping Wu yupingso@google.com
Gerrit-MessageType: comment