Change in ...coreboot[master]: mb/GA-Z170N-WIFI: Add mainboard

[Marius Genheimer (Code Review)]

Marius Genheimer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32274

Change subject: mb/GA-Z170N-WIFI: Add mainboard
......................................................................

mb/GA-Z170N-WIFI: Add mainboard

Change-Id: I0ac13e8f5ac800d1c7c21b3eab15392b9eae22fc
Signed-off-by: Marius Genheimer 
---
A src/mainboard/gigabyte/ga-z170n-wifi/Kconfig
A src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name
A src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc
A src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt
A src/mainboard/gigabyte/ga-z170n-wifi/data.vbt
A src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb
A src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c
7 files changed, 152 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32274/1

diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig
new file mode 100644
index 0000000..fb21b5e
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig
@@ -0,0 +1,42 @@
+if BOARD_GIGABYTE_Z170N_WIFI
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select USE_BLOBS
+	select ADD_FSP_BINARIES
+	select FSP_USE_REPO
+	select INTEL_GMA_ADD_VBT
+	select CONSOLE_POST
+	select ONBOARD_VGA_IS_PRIMARY
+	select HAVE_ACPI_TABLES
+	select SKYLAKE_SOC_PCH_H
+	select SOC_INTEL_SKYLAKE
+	select MAINBOARD_USES_FSP2_0
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAINBOARD_DIR
+	string
+	default "gigabyte/ga-z170n-wifi"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Z170N-WIFI"
+
+config MAINBOARD_FAMILY
+	string
+	default "Gigabyte_Z170"
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_SPD_SIZE
+	int
+	default 512 #DDR4
+
+endif
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name
new file mode 100644
index 0000000..dbabce7
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_Z170N_WIFI
+	bool "GA-Z170N-WIFI"
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc b/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc
new file mode 100644
index 0000000..63889af
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+romstage-y += pei_data.c
+
+ramstage-y += ramstage.c
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt b/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt
new file mode 100644
index 0000000..d3295d9
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Saddle Brook Skylake Reference Board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt b/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt
new file mode 100644
index 0000000..45e381c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt
Binary files differ
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb b/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb
new file mode 100644
index 0000000..717c994
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb
@@ -0,0 +1,53 @@
+chip soc/intel/skylake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 on  end # I2C #2
+		device pci 15.3 on  end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 on end # SATA
+		device pci 19.0 on  end # UART #2
+		device pci 19.1 on  end # I2C #5
+		device pci 19.2 on  end # I2C #4
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 on  end # UART #1
+		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.3 on  end # GSPI #1
+		device pci 1e.4 off  end # eMMC
+		device pci 1e.5 off  end # SDIO
+		device pci 1e.6 off  end # SDCard
+		device pci 1f.0 on
+		end # LPC Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 on end # GbE
+	end
+end
diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c b/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c
new file mode 100644
index 0000000..ac4ce95
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include "spd/spd.h"
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	mainboard_fill_dq_map_data(&pei_data->dq_map);
+	mainboard_fill_dqs_map_data(&pei_data->dqs_map);
+	mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);
+}

[Marius Genheimer (Code Review)]

Marius Genheimer has removed Martin Roth from this change.  ( https://review.coreboot.org/c/coreboot/+/32274 )

Change subject: mb/GA-Z170N-WIFI: Add mainboard
......................................................................

Removed reviewer Martin Roth.

[Marius Genheimer (Code Review)]

Marius Genheimer has removed Patrick Georgi from this change.  ( https://review.coreboot.org/c/coreboot/+/32274 )

Change subject: mb/GA-Z170N-WIFI: Add mainboard
......................................................................

Removed reviewer Patrick Georgi.