Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50036 )
Change subject: intel: Turn `DEFAULT_RCBA` into a Kconfig symbol ......................................................................
intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/rcba.h M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 29 files changed, 33 insertions(+), 44 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index cdca27a..e17c8ee 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -36,7 +36,7 @@
/* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + CONFIG_FIXED_RCBA_MMIO_BASE | 1); }
void bootblock_soc_init(void) diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 7f64219..8c5fb49 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -3,7 +3,6 @@ #include "hostbridge.asl" #include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -14,7 +13,7 @@ // This does not seem to work correctly yet - set values statically for // now. Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index fd7ce52..f2c0090 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -264,7 +264,7 @@
/* Link1: target port 0, component id 2 (ICH), link valid. */ DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
/* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647..50a1306 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h" -#include <southbridge/intel/common/rcba.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8af6eb2..c2c8143 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -511,7 +511,7 @@ reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; reg32 = DMIBAR32(DMILE2D); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02..f5d500b2 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 11d3b50..5e7f4ec 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "../i945.h" -#include <southbridge/intel/common/rcba.h>
/* Operating System Capabilities Method */ Method (_OSC, 4) @@ -38,7 +37,7 @@ //})
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b..4564ff4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -730,7 +730,7 @@ reg32 |= (1 << 0); DMIBAR32(DMILE1D) = reg32;
- DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 73242e4..c43b17b 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -2,7 +2,6 @@
#include "../ironlake.h" #include "hostbridge.asl" -#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4620c4f..2f34b0d 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -13,7 +12,7 @@ /* This does not seem to work correctly yet - set values statically for now. */
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 1e47c1f..16bcd54 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "peg.asl" -#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) // Filled by _CRS Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 33cb7ad..60ee615 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "../memmap.h" -#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -11,7 +10,7 @@ Name (_UID, 1)
Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4a033ab..8833a5e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 767d3ad..6ed3dce 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -218,7 +218,7 @@
static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index bef98fa..28337f6 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -186,7 +186,7 @@ return;
/* Verify that RCBA is still valid */ - if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) + if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE)) return;
if (RCBA32(FD) & PCH_DISABLE_XHCI) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index a14513d..5b5fe55 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -104,6 +104,10 @@ bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
+config FIXED_RCBA_MMIO_BASE + hex + default 0xfed1c000 + config FIXED_SMBUS_IO_BASE hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 712a477..4a9847a 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -3,9 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
-#ifndef __ACPI__ - -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE)
/* Root Complex Register Block */ #define RCBA 0xf0 @@ -23,10 +21,4 @@ #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-#else - -#define DEFAULT_RCBA 0xfed1c000 - -#endif /* __ACPI__ */ - #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 4d07720..4f55277 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -110,7 +110,7 @@
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { // Backbone diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 72281ea..c8a6117 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -48,7 +48,7 @@ void i82801gx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);
diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index f720505..3455acf 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -110,7 +110,7 @@
// ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 3c0f3ae..f781098 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -51,7 +51,7 @@ enable_smbus();
/* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
/* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index d6136af..53ead1c 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@
// ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 7714609..327c8fc 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -50,7 +50,7 @@ const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */ - pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
/* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378e..99fa530 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -80,7 +80,7 @@
/* Enable RCBA */ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index f5285c1..2fa4b52 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -30,7 +30,7 @@ void ibexpeak_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a878dc2..f97a5ad 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ }
// Root Complex Register Block - OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58e..c063bfb 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -7,7 +7,7 @@
static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); }
static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a87..ace8b54 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -36,7 +36,7 @@
static void pch_enable_bars(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 24a5a7e..20b9b43 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -557,9 +557,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */ - if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { + if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); - res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; + res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE;
-
Patrick Georgi (Code Review)