Change in ...coreboot[master]: src/(device/lib/soc): Remove unused variables

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29985

Change subject: src/(device/lib/soc): Remove unused variables
......................................................................

src/(device/lib/soc): Remove unused variables

When building grunt with flags set to detect variables that get a value but
then are unused, there are 7 instances that causes error (unused variable).
In most cases it's enough to simply remove the variable. In one instance,
the variable is used to receive the return of a function. For this instance,
add a debug print that will use it. On another instance, the variable will
be used depending on build options, so the variable must only be created and
set if this build option is set.

BUG=b:120260448
TEST=Build and boot grunt.

Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead
Signed-off-by: Richard Spiegel 
---
M src/device/dram/ddr3.c
M src/lib/selfboot.c
M src/soc/amd/common/block/pi/def_callouts.c
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/southbridge.c
6 files changed, 9 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29985/1

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index f27fdcb..1f5b7eb 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -136,7 +136,10 @@
    u8 reg8;
    u32 mtb;		/* medium time base */
    u32 ftb;		/* fine time base */
-	unsigned int val, param;
+	unsigned int val;
+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
+	unsigned int param;
+#endif

ret = SPD_STATUS_OK;

@@ -173,7 +176,9 @@
    	printram("  Invalid number of memory banks\n");
    	ret = SPD_STATUS_INVALID_FIELD;
    }
+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
    param = 1 << (val + 3);
+#endif
    printram("  Banks              : %u\n", param);
    /* SDRAM capacity */
    capacity_shift = reg8 & 0x0f;
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 9c52cd6..f1c2ba4 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -144,9 +144,9 @@
 {
    uint8_t *dest;
    size_t memsz;
-	struct cbfs_payload_segment *first_segment, *seg, segment;
+	struct cbfs_payload_segment *seg, segment;

-	for (first_segment = seg = cbfssegs;; ++seg) {
+	for (seg = cbfssegs;; ++seg) {
    	printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg);
    	cbfs_decode_payload_segment(&segment, seg);
    	dest = (uint8_t *)(uintptr_t)segment.load_addr;
diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c
index 0fffaf3..693c7c5 100644
--- a/src/soc/amd/common/block/pi/def_callouts.c
+++ b/src/soc/amd/common/block/pi/def_callouts.c
@@ -116,10 +116,8 @@
 {
    AGESA_STATUS Status;
    uintptr_t ResetType;
-	AMD_CONFIG_PARAMS *StdHeader;

ResetType = Data;
-	StdHeader = ConfigPtr;

/*
     * This should perform the RESET based upon the ResetType, but coreboot
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 317574b..efc948d 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -145,6 +145,7 @@

/* Allocate ACPI NVS in CBMEM */
    gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+	printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs);
 }

static void lpc_set_resources(struct device *dev)
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 749eefe..94242da 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -226,12 +226,9 @@
    acpi_header_t *ssdt;
    acpi_header_t *alib;
    acpi_header_t *ivrs;
-	acpi_hest_t *hest;
-	acpi_bert_t *bert;

/* HEST */
    current = ALIGN(current, 8);
-	hest = (acpi_hest_t *)current;
    acpi_write_hest((void *)current, acpi_fill_hest);
    acpi_add_table(rsdp, (void *)current);
    current += ((acpi_header_t *)current)->length;
@@ -249,7 +246,6 @@
    		printk(BIOS_ERR, "Error: Can't find BERT storage area\n");
    	} else {
    		current = ALIGN(current, 8);
-			bert = (acpi_bert_t *)current;
    		acpi_write_bert((void *)current, (uintptr_t)rgn, size);
    		acpi_add_table(rsdp, (void *)current);
    		current += ((acpi_header_t *)current)->length;
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 6157e50..bbebf6c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -217,13 +217,10 @@
  */
 int sb_find_wideio_range(uint16_t start, uint16_t size)
 {
-	uint32_t enable_register;
    int i, index = WIDEIO_RANGE_ERROR;
    uint16_t end, current_size, start_wideio, end_wideio;

end = start + size;
-	enable_register = pci_read_config32(SOC_LPC_DEV,
-					   LPC_IO_OR_MEM_DECODE_ENABLE);
    for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) {
    	current_size = sb_wideio_size(i);
    	if (current_size == 0)