Change in coreboot[master]: superio/nuvoton/nct5539d: Update documentation and remove DSDT
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
superio/nuvoton/nct5539d: Update documentation and remove DSDT
There seems to be no board using this, but some currently under review. Remove the DSDT, which doesn't work together with the SSDT ACPI code generation. Also update the documentation pointing to the SSDT generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/superio/index.md A Documentation/superio/nuvoton/nct5539d.md D src/superio/nuvoton/nct5539d/acpi/superio.asl 3 files changed, 10 insertions(+), 157 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38864/1
diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 053663b..81287bb 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -5,6 +5,7 @@ ## Nuvoton
- [NPCD378](nuvoton/npcd378.md) +- [NCT5539D](nuvoton/nct5539d.md)
## Common - [PNP devices](common/pnp.md) diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md new file mode 100644 index 0000000..e91ebc3 --- /dev/null +++ b/Documentation/superio/nuvoton/nct5539d.md @@ -0,0 +1,9 @@ +# NCT5539D SuperIO + +The SuperIO has the ID `0xd121` and the source can be found in +`src/superio/nuvoton/nct5539d/`. + +## For developers + +The SuperIO generates ACPI using the +[SSDT generator for generic SuperIOs](../common/ssdt.md). diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl deleted file mode 100644 index 6f49421..0000000 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* - * Include this file into a mainboard's DSDT _SB device tree and it will - * expose the NCT5539D SuperIO and some of its functionality. - * - * It allows the change of IO ports, IRQs and DMA settings on logical - * devices, disabling and reenabling logical devices. - * - * LDN State - * 0x2 SP1 Implemented, untested - * 0x5 KBC Implemented, untested - * 0x8 GPIO Implemented, untested - * 0xb HWM Implemented, untested - * - * Controllable through preprocessor defines: - * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) - * SUPERIO_PNP_BASE I/O address of the first PnP configuration register - * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. - * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. - * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. - * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. - */ - -#undef SUPERIO_CHIP_NAME -#define SUPERIO_CHIP_NAME NCT5539D -#include <superio/acpi/pnp.asl> - -#undef PNP_DEFAULT_PSC -#define PNP_DEFAULT_PSC Return (0) /* no power management */ - -Device(SUPERIO_DEV) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) - Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) - - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8, - } - IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ - - Offset (0x30), - PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ - ACT1, 1, /* Logical device activation */ - ACT2, 1, /* Logical device activation */ - ACT3, 1, /* Logical device activation */ - ACT4, 1, /* Logical device activation */ - ACT5, 1, /* Logical device activation */ - ACT6, 1, /* Logical device activation */ - ACT7, 1, /* Logical device activation */ - - Offset (0x60), - PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ - PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ - Offset (0x62), - PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ - PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ - Offset (0x64), - PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ - PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ - - Offset (0x70), - PNP_IRQ0, 8, /* First IRQ */ - Offset (0x72), - PNP_IRQ1, 8, /* Second IRQ */ - Offset (0x74), - PNP_DMA0, 8, /* DRQ */ - } - - Method (_CRS) - { - /* Announce the used I/O ports to the OS */ - Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) - }) - } - - #undef PNP_ENTER_MAGIC_1ST - #undef PNP_ENTER_MAGIC_2ND - #undef PNP_ENTER_MAGIC_3RD - #undef PNP_ENTER_MAGIC_4TH - #undef PNP_EXIT_MAGIC_1ST - #undef PNP_EXIT_SPECIAL_REG - #undef PNP_EXIT_SPECIAL_VAL - #define PNP_ENTER_MAGIC_1ST 0x87 - #define PNP_ENTER_MAGIC_2ND 0x87 - #define PNP_EXIT_MAGIC_1ST 0xaa - #include <superio/acpi/pnp_config.asl> - - -#ifdef NCT5539D_SHOW_SP1 - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 2 - #include <superio/acpi/pnp_uart.asl> -#endif - -#ifdef NCT5539D_SHOW_KBC - #undef SUPERIO_KBC_LDN - #undef SUPERIO_KBC_PS2M - #undef SUPERIO_KBC_PS2LDN - #define SUPERIO_KBC_LDN 5 - #define SUPERIO_KBC_PS2M - #include <superio/acpi/pnp_kbc.asl> -#endif - -#ifdef NCT5539D_SHOW_HWM - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #define SUPERIO_PNP_LDN 11 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #define SUPERIO_PNP_IO1 0x08, 0x08 - #define SUPERIO_PNP_IRQ0 - #include <superio/acpi/pnp_generic.asl> -#endif - -#ifdef NCT5539D_SHOW_GPIO - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #undef PNP_DEVICE_ACTIVE - #define PNP_DEVICE_ACTIVE ACT3 - #define SUPERIO_PNP_LDN 8 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #include <superio/acpi/pnp_generic.asl> -#endif -}
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... File Documentation/superio/nuvoton/nct5539d.md:
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 1: SuperIO Super I/O
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 3: SuperIO Super I/O
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 8: SuperIO Super I/O
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38864/2/Documentation/superio/nuvot... File Documentation/superio/nuvoton/nct5539d.md:
PS2: If you are going to add documentation, I would add that the datasheet for this SIO can be obtained by asking Nuvoton.
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Looks like your devicetree is broken, as there are tons of "BUG: Check your devicetree!" There's documentation how to use the SIO SSDT gen: https://doc.coreboot.org/superio/common/ssdt.html
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Looks like your devicetree is broken, as there are tons of "BUG: Check your devicetree!" There's documentation how to use the SIO SSDT gen: https://doc.coreboot.org/superio/common/ssdt.html
added ssdt option to the devicetree.cb and tested, https://drive.google.com/open?id=1eyPO_tEzJdNJ_pfDYLmsZ0R-1gJVPuNg
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2: Code-Review+2
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Looks like your devicetree is broken, as there are tons of "BUG: Check your devicetree!" There's documentation how to use the SIO SSDT gen: https://doc.coreboot.org/superio/common/ssdt.html
added ssdt option to the devicetree.cb and tested, https://drive.google.com/open?id=1eyPO_tEzJdNJ_pfDYLmsZ0R-1gJVPuNg
I see no "BUG", so it works fine?
Pavlushka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+2
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Looks like your devicetree is broken, as there are tons of "BUG: Check your devicetree!" There's documentation how to use the SIO SSDT gen: https://doc.coreboot.org/superio/common/ssdt.html
added ssdt option to the devicetree.cb and tested, https://drive.google.com/open?id=1eyPO_tEzJdNJ_pfDYLmsZ0R-1gJVPuNg
I see no "BUG", so it works fine?
To the point of "found /dev/ttyS0".
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2: Code-Review+2
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Tested, didn't go well, the system halts earlier than before. A bit lazy to create a full report but it's on the way (in few hours may be).
Looks like your devicetree is broken, as there are tons of "BUG: Check your devicetree!" There's documentation how to use the SIO SSDT gen: https://doc.coreboot.org/superio/common/ssdt.html
added ssdt option to the devicetree.cb and tested, https://drive.google.com/open?id=1eyPO_tEzJdNJ_pfDYLmsZ0R-1gJVPuNg
I see no "BUG", so it works fine?
To the point of "found /dev/ttyS0".
I can't decode the log. It looks like it worked the first time as it printed "sky login"? The earlyprintk isn't working as you only get late systemd messages. Does it work with the dsdt acpi code?
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38864/2/Documentation/superio/nuvot... File Documentation/superio/nuvoton/nct5539d.md:
PS2:
If you are going to add documentation, I would add that the datasheet for this SIO can be obtained b […]
patches accepted :-)
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 2:
(3 comments)
CB:39451 changes this file and also sets up a checkpatch test for SuperIO, proposing Super I/O. This only passed because I disabled the test during commit, because there are many, many instances of "SuperIO" in the tree, but that's something to clean up over there, not here.
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... File Documentation/superio/nuvoton/nct5539d.md:
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 1: SuperIO
Super I/O
Done
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 3: SuperIO
Super I/O
Done
https://review.coreboot.org/c/coreboot/+/38864/1/Documentation/superio/nuvot... PS1, Line 8: SuperIO
Super I/O
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
superio/nuvoton/nct5539d: Update documentation and remove DSDT
There seems to be no board using this, but some currently under review. Remove the DSDT, which doesn't work together with the SSDT ACPI code generation. Also update the documentation pointing to the SSDT generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/superio/index.md A Documentation/superio/nuvoton/nct5539d.md D src/superio/nuvoton/nct5539d/acpi/superio.asl 3 files changed, 10 insertions(+), 157 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/Documentation/superio/index.md b/Documentation/superio/index.md index 053663b..81287bb 100644 --- a/Documentation/superio/index.md +++ b/Documentation/superio/index.md @@ -5,6 +5,7 @@ ## Nuvoton
- [NPCD378](nuvoton/npcd378.md) +- [NCT5539D](nuvoton/nct5539d.md)
## Common - [PNP devices](common/pnp.md) diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md new file mode 100644 index 0000000..e91ebc3 --- /dev/null +++ b/Documentation/superio/nuvoton/nct5539d.md @@ -0,0 +1,9 @@ +# NCT5539D SuperIO + +The SuperIO has the ID `0xd121` and the source can be found in +`src/superio/nuvoton/nct5539d/`. + +## For developers + +The SuperIO generates ACPI using the +[SSDT generator for generic SuperIOs](../common/ssdt.md). diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl deleted file mode 100644 index 6f49421..0000000 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* - * Include this file into a mainboard's DSDT _SB device tree and it will - * expose the NCT5539D SuperIO and some of its functionality. - * - * It allows the change of IO ports, IRQs and DMA settings on logical - * devices, disabling and reenabling logical devices. - * - * LDN State - * 0x2 SP1 Implemented, untested - * 0x5 KBC Implemented, untested - * 0x8 GPIO Implemented, untested - * 0xb HWM Implemented, untested - * - * Controllable through preprocessor defines: - * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) - * SUPERIO_PNP_BASE I/O address of the first PnP configuration register - * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. - * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. - * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. - * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. - */ - -#undef SUPERIO_CHIP_NAME -#define SUPERIO_CHIP_NAME NCT5539D -#include <superio/acpi/pnp.asl> - -#undef PNP_DEFAULT_PSC -#define PNP_DEFAULT_PSC Return (0) /* no power management */ - -Device(SUPERIO_DEV) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) - Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) - - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - PNP_ADDR_REG, 8, - PNP_DATA_REG, 8, - } - IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ - - Offset (0x30), - PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ - ACT1, 1, /* Logical device activation */ - ACT2, 1, /* Logical device activation */ - ACT3, 1, /* Logical device activation */ - ACT4, 1, /* Logical device activation */ - ACT5, 1, /* Logical device activation */ - ACT6, 1, /* Logical device activation */ - ACT7, 1, /* Logical device activation */ - - Offset (0x60), - PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ - PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ - Offset (0x62), - PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ - PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ - Offset (0x64), - PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ - PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ - - Offset (0x70), - PNP_IRQ0, 8, /* First IRQ */ - Offset (0x72), - PNP_IRQ1, 8, /* Second IRQ */ - Offset (0x74), - PNP_DMA0, 8, /* DRQ */ - } - - Method (_CRS) - { - /* Announce the used I/O ports to the OS */ - Return (ResourceTemplate () { - IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) - }) - } - - #undef PNP_ENTER_MAGIC_1ST - #undef PNP_ENTER_MAGIC_2ND - #undef PNP_ENTER_MAGIC_3RD - #undef PNP_ENTER_MAGIC_4TH - #undef PNP_EXIT_MAGIC_1ST - #undef PNP_EXIT_SPECIAL_REG - #undef PNP_EXIT_SPECIAL_VAL - #define PNP_ENTER_MAGIC_1ST 0x87 - #define PNP_ENTER_MAGIC_2ND 0x87 - #define PNP_EXIT_MAGIC_1ST 0xaa - #include <superio/acpi/pnp_config.asl> - - -#ifdef NCT5539D_SHOW_SP1 - #undef SUPERIO_UART_LDN - #undef SUPERIO_UART_DDN - #undef SUPERIO_UART_PM_REG - #undef SUPERIO_UART_PM_VAL - #undef SUPERIO_UART_PM_LDN - #define SUPERIO_UART_LDN 2 - #include <superio/acpi/pnp_uart.asl> -#endif - -#ifdef NCT5539D_SHOW_KBC - #undef SUPERIO_KBC_LDN - #undef SUPERIO_KBC_PS2M - #undef SUPERIO_KBC_PS2LDN - #define SUPERIO_KBC_LDN 5 - #define SUPERIO_KBC_PS2M - #include <superio/acpi/pnp_kbc.asl> -#endif - -#ifdef NCT5539D_SHOW_HWM - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #define SUPERIO_PNP_LDN 11 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #define SUPERIO_PNP_IO1 0x08, 0x08 - #define SUPERIO_PNP_IRQ0 - #include <superio/acpi/pnp_generic.asl> -#endif - -#ifdef NCT5539D_SHOW_GPIO - #undef SUPERIO_PNP_HID - #undef SUPERIO_PNP_LDN - #undef SUPERIO_PNP_DDN - #undef SUPERIO_PNP_PM_REG - #undef SUPERIO_PNP_PM_VAL - #undef SUPERIO_PNP_PM_LDN - #undef SUPERIO_PNP_IO0 - #undef SUPERIO_PNP_IO1 - #undef SUPERIO_PNP_IO2 - #undef SUPERIO_PNP_IRQ0 - #undef SUPERIO_PNP_IRQ1 - #undef SUPERIO_PNP_DMA - #undef PNP_DEVICE_ACTIVE - #define PNP_DEVICE_ACTIVE ACT3 - #define SUPERIO_PNP_LDN 8 - #define SUPERIO_PNP_IO0 0x08, 0x08 - #include <superio/acpi/pnp_generic.asl> -#endif -}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38864 )
Change subject: superio/nuvoton/nct5539d: Update documentation and remove DSDT ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1259 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1258 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1257
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Felix Held (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)
-
Pavlushka (Code Review)