Change in coreboot[master]: soc/intel/tigerlake: Update interrupt setting

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=none
BRANCH=none
TEST=Build and boot OS and login OS console in ripto/voteer
Without this change, we can't login due to mismatch interupt setting

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/1

diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index 62520b1..116b9a3 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -19,6 +19,7 @@
    /* D31:HDA, SMBUS, TraceHUB */
    Package(){0x001FFFFF, 3, 0, HDA_IRQ },
    Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+	Package(){0x001FFFFF, 6, 0, GBE_IRQ },
    Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
    /* D30: UART0, UART1, SPI0, SPI1 */
    Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
@@ -64,8 +65,7 @@
    /* D18: ISH, SPI2 */
    Package(){0x0012FFFF, 0, 0, ISH_IRQ },
    Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+	/* D16: TCH0, TCH1 */
    Package(){0x0010FFFF, 6, 0, THC0_IRQ },
    Package(){0x0010FFFF, 7, 0, THC1_IRQ },
    /* D13: xHCI, xDCI */
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index 01ee10b..e494980 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -11,20 +11,21 @@
 #define PCH_IRQ11	11

#define LPSS_I2C0_IRQ	27
-#define LPSS_I2C1_IRQ	28
+#define LPSS_I2C1_IRQ 	40
 #define LPSS_I2C2_IRQ	29
 #define LPSS_I2C3_IRQ	30
 #define LPSS_I2C4_IRQ	31
 #define LPSS_I2C5_IRQ	32
 #define LPSS_SPI0_IRQ	36
 #define LPSS_SPI1_IRQ	37
-#define LPSS_SPI2_IRQ	18
-#define LPSS_SPI3_IRQ	23
-#define LPSS_UART0_IRQ	34
-#define LPSS_UART1_IRQ	35
+#define LPSS_SPI2_IRQ	34
+#define LPSS_SPI3_IRQ 	43
+#define LPSS_UART0_IRQ 	16
+#define LPSS_UART1_IRQ 	17
 #define LPSS_UART2_IRQ	33

#define HDA_IRQ		16
+#define GBE_IRQ		16
 #define SMBUS_IRQ	16
 #define TRACEHUB_IRQ	16

@@ -49,8 +50,8 @@

#define CNVI_BT_IRQ	18

-#define THC0_IRQ	16
-#define THC1_IRQ	17
+#define THC0_IRQ	23
+#define THC1_IRQ	22

#define ISH_IRQ		16

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/irq.h:

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 14: #define LPSS_I2C1_IRQ 	40
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 22: #define LPSS_SPI3_IRQ 	43
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 23: #define LPSS_UART0_IRQ 	16
please, no space before tabs

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 24: #define LPSS_UART1_IRQ 	17
please, no space before tabs

[Wonkyu Kim (Code Review)]

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40872

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=none
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/2

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40872

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/3

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40872

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/4

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

Patch Set 4:

(4 comments)

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/irq.h:

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 14: #define LPSS_I2C1_IRQ 	40
> please, no space before tabs

Done

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 22: #define LPSS_SPI3_IRQ 	43
> please, no space before tabs

Done

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 23: #define LPSS_UART0_IRQ 	16
> please, no space before tabs

Done

https://review.coreboot.org/c/coreboot/+/40872/1/src/soc/intel/tigerlake/inc... 
PS1, Line 24: #define LPSS_UART1_IRQ 	17
> please, no space before tabs

Done

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

Patch Set 4: Code-Review+1

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded a new patch set (#5) to the change originally created by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40872/5

[Dossym Nurmukhanov (Code Review)]

Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

Patch Set 5: Code-Review+2

[Stefan Reinauer (Code Review)]

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

soc/intel/tigerlake: Update interrupt setting

Update interrupt setting based on latest FSP(3163.01)

Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c

BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer.  Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140

Signed-off-by: Wonkyu Kim 
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/include/soc/irq.h
2 files changed, 10 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wonkyu Kim: Looks good to me, but someone else must approve
  Dossym Nurmukhanov: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index 62520b1..116b9a3 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -19,6 +19,7 @@
    /* D31:HDA, SMBUS, TraceHUB */
    Package(){0x001FFFFF, 3, 0, HDA_IRQ },
    Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+	Package(){0x001FFFFF, 6, 0, GBE_IRQ },
    Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
    /* D30: UART0, UART1, SPI0, SPI1 */
    Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
@@ -64,8 +65,7 @@
    /* D18: ISH, SPI2 */
    Package(){0x0012FFFF, 0, 0, ISH_IRQ },
    Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+	/* D16: TCH0, TCH1 */
    Package(){0x0010FFFF, 6, 0, THC0_IRQ },
    Package(){0x0010FFFF, 7, 0, THC1_IRQ },
    /* D13: xHCI, xDCI */
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index 01ee10b..8763abb 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -11,20 +11,21 @@
 #define PCH_IRQ11	11

#define LPSS_I2C0_IRQ	27
-#define LPSS_I2C1_IRQ	28
+#define LPSS_I2C1_IRQ	40
 #define LPSS_I2C2_IRQ	29
 #define LPSS_I2C3_IRQ	30
 #define LPSS_I2C4_IRQ	31
 #define LPSS_I2C5_IRQ	32
 #define LPSS_SPI0_IRQ	36
 #define LPSS_SPI1_IRQ	37
-#define LPSS_SPI2_IRQ	18
-#define LPSS_SPI3_IRQ	23
-#define LPSS_UART0_IRQ	34
-#define LPSS_UART1_IRQ	35
+#define LPSS_SPI2_IRQ	34
+#define LPSS_SPI3_IRQ	43
+#define LPSS_UART0_IRQ	16
+#define LPSS_UART1_IRQ	17
 #define LPSS_UART2_IRQ	33

#define HDA_IRQ		16
+#define GBE_IRQ		16
 #define SMBUS_IRQ	16
 #define TRACEHUB_IRQ	16

@@ -49,8 +50,8 @@

#define CNVI_BT_IRQ	18

-#define THC0_IRQ	16
-#define THC1_IRQ	17
+#define THC0_IRQ	23
+#define THC1_IRQ	22

#define ISH_IRQ		16

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40872 )

Change subject: soc/intel/tigerlake: Update interrupt setting
......................................................................

Patch Set 6:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3207
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3206
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3205
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3204

Please note: This test is under development and might not be accurate at all!