[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Adjust eSPI GPIO

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86919?usp=email )

Change subject: mb/starlabs/starbook/adl_n: Adjust eSPI GPIO
......................................................................

mb/starlabs/starbook/adl_n: Adjust eSPI GPIO

Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.

Change-Id: I7da5cf493a676ea106ab94fcb377bc8a29b72990
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86919
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
index 1c17b97..54f5971 100644
--- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c
@@ -157,7 +157,7 @@
    /* C5:		Boot Strap		Weak Internal PD 20K
    			Low:	ESPI
    			High:	Disabled			*/
-	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_GPO(GPP_C5, 0, PLTRST),
    /* C6:		SML 1 Clock					*/
    PAD_NC(GPP_C6, NONE),
    /* C7:		SML 1 Data					*/