[S] Change in coreboot[main]: doc/internals/devicetree_language: multiple segment groups supported

[Maximilian Brune (Code Review)]

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87206?usp=email )

Change subject: doc/internals/devicetree_language: multiple segment groups supported
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doc/internals/devicetree_language: multiple segment groups supported

coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.

Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer 
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
Reviewed-by: Maximilian Brune 
---
M Documentation/internals/devicetree_language.md
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  Felix Singer: Looks good to me, approved
  build bot (Jenkins): Verified
  Maximilian Brune: Looks good to me, approved

diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index ab1b646..43a2233 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -973,11 +973,11 @@
 Resources for all PCI devices are assigned automatically, or must be
 assigned in code if they're non-standard.

-Currently, only a single segment is supported, but there is work to make
-multiple different segments supported, each with a bus 0. Because the
-bus is not specified, It's assumed that all pci devices that are not
-behind a pci bridge device are on bus 0. If there are additional pci
-busses in a chip, they can be added behind their bridge device.
+Only a single segment group is supported per domain, but there can be multiple
+domains to support the case of multiple segment groups, each with a bus 0.
+Because the bus is not specified, It's assumed that all pci devices that are
+not behind a pci bridge device are on bus 0. If there are additional pci busses
+in a chip, they can be added behind their bridge device.

Examples: