Attention is currently required from: Angel Pons, Federico Amedeo Izzo.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email )
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ......................................................................
Patch Set 10: Code-Review+1
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82010/comment/5108ad87_162bc007 : PS10, Line 57: Patchset 5: Re-enabled dptf, added default options to Kconfig. : Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works : Pa It's not needed to document the changes of each patchset. Please remove.
File src/mainboard/aoostar/wtr_r1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/82010/comment/505e5faf_b7d291bb : PS2, Line 1:
Remove blank line
Done
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/9398383e_4a118b0b : PS10, Line 67: register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C : register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # microSD card reader : register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # USB2 Type A upper : register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB2 Type A lower : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A upper : register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A lower : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # microSD card reader : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A lower : Rewrite as:
``` register "usb2_ports" = "{ [0] = USB2_PORT_TYPE_C(OC0), /* Type-C */ ... }" ```
https://review.coreboot.org/c/coreboot/+/82010/comment/a03c0a11_58f97814 : PS10, Line 114: device ref pcie_rp3 on : register "pch_pcie_rp[PCH_RP(3)]" = "{ : .clk_src = 2, : .clk_req = 2, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp7 on : register "pch_pcie_rp[PCH_RP(7)]" = "{ : .clk_src = 3, : .clk_req = 3, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp9 on : register "pch_pcie_rp[PCH_RP(9)]" = "{ : .clk_src = 0, : .clk_req = 0, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end : device ref pcie_rp10 on : register "pch_pcie_rp[PCH_RP(10)]" = "{ : .clk_src = 1, : .clk_req = 1, : .flags = PCIE_RP_CLK_REQ_DETECT, : }" : end For accessible ports, add SMBIOS information with `smbios_slot_desc`. The tree provides several usage examples. For the other ports, add a short comment on how they are used.
File src/mainboard/aoostar/wtr_r1/gpio.h:
PS2:
Remove comments to GPIOs which are configured with PAD_NC.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/d4127db3_2736a9df : PS2, Line 222: /* ------- GPIO Group PCIe vGPIO ------- */
Remove the superfluous comments below.
Done