Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69078 )
Change subject: cbmem_top_chipset: Change the return value to uintptr_t ......................................................................
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/mainboard/emulation/qemu-power9/cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sc7280/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ti/am335x/cbmem.c M src/soc/ucb/riscv/cbmem.c M tests/lib/coreboot_table-test.c M tests/lib/imd_cbmem-test.c 37 files changed, 86 insertions(+), 74 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/1
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index f60239a..c8bcfec 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -93,8 +93,8 @@ halt(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return restore_top_of_low_cacheable(); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..b725aad 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -3,10 +3,10 @@ #include <cbmem.h> #include <fsp/util.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return (uintptr_t)range_entry_end(&tolum); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5b5191a..911291a 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -65,7 +65,7 @@ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same * implementation as used in romstage will be used. */ -void *cbmem_top_chipset(void); +uintptr_t cbmem_top_chipset(void);
/* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index 6b6ac72..389ff4e 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -4,7 +4,7 @@ #include <ramdetect.h> #include <symbols.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443..5c423a0 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352..efe83c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -41,7 +41,7 @@ return tomk; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0;
@@ -56,7 +56,7 @@ smm_region(&top, &smm_size); }
- return (void *)top; + return top; }
/* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8..f14a5e2 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -2,10 +2,10 @@
#include <cbmem.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); + uintptr_t ptr = (uintptr_t)((1ULL << 32) - 1048576); return ptr; } diff --git a/src/mainboard/emulation/qemu-power9/cbmem.c b/src/mainboard/emulation/qemu-power9/cbmem.c index 1b7b690..11e48bd 100644 --- a/src/mainboard/emulation/qemu-power9/cbmem.c +++ b/src/mainboard/emulation/qemu-power9/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <ramdetect.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); + return (probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb38..2ba7c80 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -104,10 +104,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfec..6b75caa 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -54,9 +54,9 @@ return tolum; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..5cee1b4 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -8,7 +8,7 @@ #include <program_loading.h> #include "i440bx.h"
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -39,7 +39,7 @@ * * Source: 440BX datasheet, pages 3-28 thru 3-29. */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + uintptr_t tom = pci_read_config8(NB, DRB7) * 8 * MiB;
int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; /* T_SZ and TSEG_EN */ @@ -48,7 +48,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; }
void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1fa0358..96dee76 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -57,10 +57,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
/* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..bdb76c1 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -22,9 +22,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)northbridge_get_tseg_base(); + return northbridge_get_tseg_base(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35..55d7046 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -73,9 +73,9 @@ * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); + return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
}
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544..ac95ab5 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -54,9 +54,9 @@ return tolum; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)top_of_low_usable_memory(); + return top_of_low_usable_memory(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902..5079756 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -71,10 +71,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index f015740..8de3515 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <amdblocks/biosram.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM);
@@ -20,7 +20,7 @@ return 0;
/* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE, 8 * MiB); }
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16..0b0c717 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -5,8 +5,8 @@ #include <soc/sdram.h> #include <symbols.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return (uintptr_t)_dram + (sdram_size_mb() - 1) * MiB; } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..43b96c1 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -16,9 +16,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 4a791ef..3c3ad74 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -19,7 +19,7 @@ *size = smm_region_size(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +53,5 @@ */
smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0..98c8016 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -29,9 +29,9 @@ return tom; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e9..0ca9e6b 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -7,7 +7,7 @@
#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f06..b38a763 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -4,7 +4,7 @@ #include <soc/display.h> #include <soc/sdram.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b2226..a56f150 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/addressmap.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr;
@@ -19,5 +19,5 @@ addr = end_mib << 20; }
- return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a..e3f4a3e 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -21,5 +21,5 @@ if (cbmem_backing_store_ready == 0) return NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf8..97f5acd 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -10,7 +10,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -22,5 +22,5 @@ if (cbmem_backing_store_ready == 0) return NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b..c5ddb17 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -2,7 +2,7 @@
#include <cbmem.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return (uintptr_t)(3 * GiB); } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37..47cd198 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -2,7 +2,7 @@
#include <cbmem.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)(4 * GiB); } diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c index 4b9eb37..47cd198 100644 --- a/src/soc/qualcomm/sc7280/cbmem.c +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -2,7 +2,7 @@
#include <cbmem.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return (uintptr_t)(4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114..3019486e 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -6,8 +6,8 @@ #include <soc/sdram.h> #include <symbols.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80..e2b58ab 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)(get_fb_base_kb() * KiB); } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80..e2b58ab 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <soc/cpu.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (uintptr_t)(get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af04130..81db74c 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -6,8 +6,8 @@ #include <soc/sdram.h> #include <symbols.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c index 3765874..215d48b 100644 --- a/src/soc/ti/am335x/cbmem.c +++ b/src/soc/ti/am335x/cbmem.c @@ -3,7 +3,7 @@ #include <cbmem.h> #include <symbols.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443..5c423a0 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -4,7 +4,7 @@ #include <symbols.h> #include <ramdetect.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 5257552..b774c97 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -264,9 +264,9 @@ }
extern uintptr_t _cbmem_top_ptr; -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; }
#define CBMEM_SIZE (64 * KiB) diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c index fe25285..e345c84 100644 --- a/tests/lib/imd_cbmem-test.c +++ b/tests/lib/imd_cbmem-test.c @@ -36,9 +36,9 @@ function_called(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr; }
static void *get_cbmem_ptr(void)
-
Elyes Haouas (Code Review)