Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Nico Huber (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Simon Yang, Angel Pons, Kane Chen, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 28: Code-Review+2

(2 comments)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/60009/comment/758b2f62_a2d95a68 
PS28, Line 411: FSP will use the value to program clock frequency for core display if GOP
              : 	 * is not run. Ex: the Chromebook normal mode.
              : 	 * For the cases GOP is run, GOP will be in charge of the related register
              : 	 * settings.
This is a very nice comment. IMO, exactly the kind of information that
the UPD comments in FSP headers always lack.

(I've been pocking Intel to document the UPDs for years but they don't
seem interested :-/ )

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/be47b42a_b3f2bc82 
PS21, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> sorry for missed the comment and thank you for your kindly remind. […]

Looks done