Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48575
to review the following change.
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/48575/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 782f3dc..ad7c4ab 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -105,9 +105,6 @@ .tdp_pl2_override = 60, }"
- # Power Limit Related - register "PowerLimit4" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3eb72fa..c9519cd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -303,7 +303,7 @@
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8b545ea..8d93ac0 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -87,9 +87,6 @@ /* TCC activation offset */ uint32_t tcc_offset;
- /* Package PL4 power limit in Watts */ - u32 PowerLimit4; - /* Whether to ignore VT-d support of the SKU */ int ignore_vtd;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48575 )
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48575 )
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
Patch Set 2: Code-Review+2
Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48575 )
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
Patch Set 2:
(1 comment)
core
https://review.coreboot.org/c/coreboot/+/48575/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/48575/2/src/soc/intel/skylake/chip.... PS2, Line 306: tconfig->PowerLimit4 = 0 coreboot configures PL4 in `soc/intel/common/block/power_limit/power_limit.c`. FSP does not "lock" this (`PowerLimit4Lock = 0`), so can this be dropped entirely?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48575 )
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48575/2/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/48575/2/src/soc/intel/skylake/chip.... PS2, Line 306: tconfig->PowerLimit4 = 0
coreboot configures PL4 in `soc/intel/common/block/power_limit/power_limit.c`. […]
I'm preserving the original behavior with this patch, since I can't test the consequences of removing this write entirely.
If anyone wants to drop it, please do so in a different patch. Thanks.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48575 )
Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting ......................................................................
soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 1 insertion(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 782f3dc..ad7c4ab 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -105,9 +105,6 @@ .tdp_pl2_override = 60, }"
- # Power Limit Related - register "PowerLimit4" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3eb72fa..c9519cd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -303,7 +303,7 @@
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 67739a4..4d92410 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -87,9 +87,6 @@ /* TCC activation offset */ uint32_t tcc_offset;
- /* Package PL4 power limit in Watts */ - u32 PowerLimit4; - /* Whether to ignore VT-d support of the SKU */ int ignore_vtd;
-
Angel Pons (Code Review) -
Benjamin Doron (Code Review)
-
Furquan Shaikh (Code Review)
-
Michael Niewöhner (Code Review)