[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48575 )

Change subject: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
......................................................................

soc/intel/skylake: Drop always-zero PowerLimit4 dt setting

Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.

Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
3 files changed, 1 insertion(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 782f3dc..ad7c4ab 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -105,9 +105,6 @@
    	.tdp_pl2_override = 60,
    }"

-	# Power Limit Related
-	register "PowerLimit4" = "0"
-
    # Lock Down
    register "common_soc_config" = "{
    .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 3eb72fa..c9519cd 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -303,7 +303,7 @@

tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
    tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
-	tconfig->PowerLimit4 = config->PowerLimit4;
+	tconfig->PowerLimit4 = 0;
    /*
     * To disable HECI, the Psf needs to be left unlocked
     * by FSP till end of post sequence. Based on the devicetree
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 67739a4..4d92410 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -87,9 +87,6 @@
    /* TCC activation offset */
    uint32_t tcc_offset;

-	/* Package PL4 power limit in Watts */
-	u32 PowerLimit4;
-
    /* Whether to ignore VT-d support of the SKU */
    int ignore_vtd;