[S] Change in coreboot[master]: mb/google/rex: Configure `SLP_S0_GATE_R` lowby default

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70196 )

Change subject: mb/google/rex: Configure `SLP_S0_GATE_R` lowby default
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mb/google/rex: Configure `SLP_S0_GATE_R` lowby default

This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SKL_S0_L` signal is `low` while
the system is in S0ix. Having `SLP_S0_GATE_R` configured to `high`
makes `SYS_SLP_S0IX_L` remain `high` always and repo the wrong
system state to EC.

BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.

Signed-off-by: Subrata Banik 
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
---
M src/mainboard/google/rex/variants/rex0/gpio.c
1 file changed, 20 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/1

diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c
index ecda8bf..b76142a 100644
--- a/src/mainboard/google/rex/variants/rex0/gpio.c
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -316,7 +316,7 @@
    /* GPP_H13 : [] ==> CPU_C10_GATE_L */
    PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
    /* GPP_H14 : [] ==> SLP_S0_GATE_R */
-	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
    /* GPP_H15 : net NC is not present in the given design */
    PAD_NC(GPP_H15, NONE),
    /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/